generale_map.map

simple thermometr in vhdl

Release 9.2i Map J.36
Xilinx Map Application Log File for Design 'generale'

Design Information
------------------
Command Line   : C:\Xilinx92i\bin\nt\map.exe -ise C:/Documents and
Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA/VGAterm/VGAterm.ise
-intstyle ise -p xc2s50-tq144-5 -cm area -pr b -k 4 -c 100 -tx off -o
generale_map.ncd generale.ngd generale.pcf 
Target Device  : xc2s50
Target Package : tq144
Target Speed   : -5
Mapper Version : spartan2 -- $Revision: 1.36 $
Mapped Date    : Sun Dec 02 20:42:29 2007

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Total Number Slice Registers:     491 out of  1,536   31%
    Number used as Flip Flops:                    474
    Number used as Latches:                        17
  Number of 4 input LUTs:         1,235 out of  1,536   80%
Logic Distribution:
    Number of occupied Slices:                         753 out of    768   98%
    Number of Slices containing only related logic:    753 out of    753  100%
    Number of Slices containing unrelated logic:         0 out of    753    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:        1,293 out of  1,536   84%
      Number used as logic:                     1,235
      Number used as a route-thru:                 56
      Number used as Shift registers:               2
   Number of bonded IOBs:             9 out of     92    9%
      IOB Flip Flops:                               3
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            1
Total equivalent gate count for design:  12,686
Additional JTAG gate count for IOBs:  480
Peak Memory Usage:  132 MB
Total REAL time to MAP completion:  6 secs 
Total CPU time to MAP completion:   4 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "generale_map.mrp" for details.