at91sam9263.h

AT91SAM9263 code for I2C based ADC and DAC

#define US0_THR		(volatile unsigned int *)0xFFF8C01C // (US0) Transmitter Holding Register
#define US0_MR		(volatile unsigned int *)0xFFF8C004 // (US0) Mode Register
#define US0_RHR		(volatile unsigned int *)0xFFF8C018 // (US0) Receiver Holding Register
#define US0_CSR		(volatile unsigned int *)0xFFF8C014 // (US0) Channel Status Register
#define US0_IMR		(volatile unsigned int *)0xFFF8C010 // (US0) Interrupt Mask Register
#define US0_IDR		(volatile unsigned int *)0xFFF8C00C // (US0) Interrupt Disable Register
#define US0_FIDI		(volatile unsigned int *)0xFFF8C040 // (US0) FI_DI_Ratio Register
#define US0_CR		(volatile unsigned int *)0xFFF8C000 // (US0) Control Register
#define US0_IER		(volatile unsigned int *)0xFFF8C008 // (US0) Interrupt Enable Register
#define US0_TTGR		(volatile unsigned int *)0xFFF8C028 // (US0) Transmitter Time-guard Register
#define US0_BRGR		(volatile unsigned int *)0xFFF8C020 // (US0) Baud Rate Generator Register
#define US0_IF		(volatile unsigned int *)0xFFF8C04C // (US0) IRDA_FILTER Register
// ========== Register definition for PDC_US0 peripheral ========== 
#define US0_TNPR		(volatile unsigned int *)0xFFF8C118 // (PDC_US0) Transmit Next Pointer Register
#define US0_PTSR		(volatile unsigned int *)0xFFF8C124 // (PDC_US0) PDC Transfer Status Register
#define US0_PTCR		(volatile unsigned int *)0xFFF8C120 // (PDC_US0) PDC Transfer Control Register
#define US0_RNCR		(volatile unsigned int *)0xFFF8C114 // (PDC_US0) Receive Next Counter Register
#define US0_RCR		(volatile unsigned int *)0xFFF8C104  // (PDC_US0) Receive Counter Register
#define US0_TNCR		(volatile unsigned int *)0xFFF8C11C // (PDC_US0) Transmit Next Counter Register
#define US0_TCR		(volatile unsigned int *)0xFFF8C10C  // (PDC_US0) Transmit Counter Register
#define US0_RNPR		(volatile unsigned int *)0xFFF8C110 // (PDC_US0) Receive Next Pointer Register
#define US0_RPR		(volatile unsigned int *)0xFFF8C100  // (PDC_US0) Receive Pointer Register
#define US0_TPR		(volatile unsigned int *)0xFFF8C108  // (PDC_US0) Transmit Pointer Register

// ========== Register definition for PMC peripheral ========== 
#define PMC_PCER		(volatile unsigned int *)0xFFFFFC10 // (PMC) Peripheral Clock Enable Register
#define PMC_PCKR		(volatile unsigned int *)0xFFFFFC40 // (PMC) Programmable Clock Register
#define PMC_MCKR		(volatile unsigned int *)0xFFFFFC30 // (PMC) Master Clock Register
#define PMC_PLLAR		(volatile unsigned int *)0xFFFFFC28 // (PMC) PLL A Register
#define PMC_PCDR		(volatile unsigned int *)0xFFFFFC14 // (PMC) Peripheral Clock Disable Register
#define PMC_SCSR		(volatile unsigned int *)0xFFFFFC08 // (PMC) System Clock Status Register
#define PMC_MCFR		(volatile unsigned int *)0xFFFFFC24 // (PMC) Main Clock  Frequency Register
#define PMC_IMR		(volatile unsigned int *)0xFFFFFC6C // (PMC) Interrupt Mask Register
#define PMC_IER		(volatile unsigned int *)0xFFFFFC60 // (PMC) Interrupt Enable Register
#define PMC_MOR		(volatile unsigned int *)0xFFFFFC20 // (PMC) Main Oscillator Register
#define PMC_IDR		(volatile unsigned int *)0xFFFFFC64 // (PMC) Interrupt Disable Register
#define PMC_PLLBR		(volatile unsigned int *)0xFFFFFC2C // (PMC) PLL B Register
#define PMC_SCDR		(volatile unsigned int *)0xFFFFFC04 // (PMC) System Clock Disable Register
#define PMC_PCSR		(volatile unsigned int *)0xFFFFFC18 // (PMC) Peripheral Clock Status Register
#define PMC_SCER		(volatile unsigned int *)0xFFFFFC00 // (PMC) System Clock Enable Register
#define PMC_SR		(volatile unsigned int *)0xFFFFFC68 // (PMC) Status Register

#define WDTC_WDMR			(volatile unsigned int *)0xFFFFFD44 // Watchdog timer mode Register

// ========== Register definition for SMC0 peripheral ========== 
#define SMC0_CYCLE6	(volatile unsigned int *)0xFFFFE468 // (SMC0)  Cycle Register for CS 6
#define SMC0_SETUP6	(volatile unsigned int *)0xFFFFE460 // (SMC0)  Setup Register for CS 6
#define SMC0_PULSE3	(volatile unsigned int *)0xFFFFE434 // (SMC0)  Pulse Register for CS 3
#define SMC0_CYCLE1	(volatile unsigned int *)0xFFFFE418 // (SMC0)  Cycle Register for CS 1
#define SMC0_SETUP5	(volatile unsigned int *)0xFFFFE450 // (SMC0)  Setup Register for CS 5
#define SMC0_CYCLE7	(volatile unsigned int *)0xFFFFE478 // (SMC0)  Cycle Register for CS 7
#define SMC0_PULSE0	(volatile unsigned int *)0xFFFFE404 // (SMC0)  Pulse Register for CS 0
#define SMC0_CYCLE5	(volatile unsigned int *)0xFFFFE458 // (SMC0)  Cycle Register for CS 5
#define SMC0_MODE0	(volatile unsigned int *)0xFFFFE40C // (SMC0)  Control Register for CS 0
#define SMC0_SETUP7	(volatile unsigned int *)0xFFFFE470 // (SMC0)  Setup Register for CS 7
#define SMC0_MODE4	(volatile unsigned int *)0xFFFFE44C // (SMC0)  Control Register for CS 4
#define SMC0_MODE1	(volatile unsigned int *)0xFFFFE41C // (SMC0)  Control Register for CS 1
#define SMC0_CYCLE2	(volatile unsigned int *)0xFFFFE428 // (SMC0)  Cycle Register for CS 2
#define SMC0_PULSE7	(volatile unsigned int *)0xFFFFE474 // (SMC0)  Pulse Register for CS 7
#define SMC0_PULSE6	(volatile unsigned int *)0xFFFFE464 // (SMC0)  Pulse Register for CS 6
#define SMC0_CYCLE4	(volatile unsigned int *)0xFFFFE448 // (SMC0)  Cycle Register for CS 4
#define SMC0_CYCLE0	(volatile unsigned int *)0xFFFFE408 // (SMC0)  Cycle Register for CS 0
#define SMC0_MODE6	(volatile unsigned int *)0xFFFFE46C // (SMC0)  Control Register for CS 6
#define SMC0_MODE5	(volatile unsigned int *)0xFFFFE45C // (SMC0)  Control Register for CS 5
#define SMC0_SETUP0	(volatile unsigned int *)0xFFFFE400 // (SMC0)  Setup Register for CS 0
#define SMC0_SETUP4	(volatile unsigned int *)0xFFFFE440 // (SMC0)  Setup Register for CS 4
#define SMC0_PULSE1	(volatile unsigned int *)0xFFFFE414 // (SMC0)  Pulse Register for CS 1
#define SMC0_MODE2	(volatile unsigned int *)0xFFFFE42C // (SMC0)  Control Register for CS 2
#define SMC0_SETUP2	(volatile unsigned int *)0xFFFFE420 // (SMC0)  Setup Register for CS 2
#define SMC0_MODE3	(volatile unsigned int *)0xFFFFE43C // (SMC0)  Control Register for CS 3
#define SMC0_SETUP3	(volatile unsigned int *)0xFFFFE430 // (SMC0)  Setup Register for CS 3
#define SMC0_MODE7	(volatile unsigned int *)0xFFFFE47C // (SMC0)  Control Register for CS 7
#define SMC0_PULSE5	(volatile unsigned int *)0xFFFFE454 // (SMC0)  Pulse Register for CS 5
#define SMC0_PULSE4	(volatile unsigned int *)0xFFFFE444 // (SMC0)  Pulse Register for CS 4
#define SMC0_PULSE2	(volatile unsigned int *)0xFFFFE424 // (SMC0)  Pulse Register for CS 2
#define SMC0_CYCLE3	(volatile unsigned int *)0xFFFFE438 // (SMC0)  Cycle Register for CS 3
#define SMC0_SETUP1	(volatile unsigned int *)0xFFFFE410 // (SMC0)  Setup Register for CS 1


// ========== Register definition for EBI0 peripheral ========== 
#define EBI0_DUMMY		(volatile unsigned int *)0xFFFFE200 // (EBI0) Dummy register - Do not use

// ========== Register definition for SDRAMC0 peripheral ========== 
#define SDRAMC0_MDR		(volatile unsigned int *)0xFFFFE224 // (SDRAMC0) SDRAM Memory Device Register
#define SDRAMC0_IDR		(volatile unsigned int *)0xFFFFE218 // (SDRAMC0) SDRAM Controller Interrupt Disable Register
#define SDRAMC0_IMR		(volatile unsigned int *)0xFFFFE21C // (SDRAMC0) SDRAM Controller Interrupt Mask Register
#define SDRAMC0_ISR		(volatile unsigned int *)0xFFFFE220 // (SDRAMC0) SDRAM Controller Interrupt Mask Register
#define SDRAMC0_HSR		(volatile unsigned int *)0xFFFFE20C // (SDRAMC0) SDRAM Controller High Speed Register
#define SDRAMC0_TR		(volatile unsigned int *)0xFFFFE204 // (SDRAMC0) SDRAM Controller Refresh Timer Register
#define SDRAMC0_CR		(volatile unsigned int *)0xFFFFE208 // (SDRAMC0) SDRAM Controller Configuration Register
#define SDRAMC0_MR		(volatile unsigned int *)0xFFFFE200 // (SDRAMC0) SDRAM Controller Mode Register
#define SDRAMC0_LPR		(volatile unsigned int *)0xFFFFE210 // (SDRAMC0) SDRAM Controller Low Power Register
#define SDRAMC0_IER		(volatile unsigned int *)0xFFFFE214 // (SDRAMC0) SDRAM Controller Interrupt Enable Register
// ========== Register definition for CCFG peripheral ========== 
#define CCFG_MATRIXVERSION	(volatile unsigned int *)0xFFFFEDFC // (CCFG)  Version Register
#define CCFG_TCMR			(volatile unsigned int *)0xFFFFED14 // (CCFG)  TCM configuration
#define EBI0_CSA			(volatile unsigned int *)0xFFFFED20 // (CCFG)  EBI0 Chip Select Assignement Register
#define EBI1_CSA			(volatile unsigned int *)0xFFFFED24 // (CCFG)  EBI1 Chip Select Assignement Register





/* CKGR_MOR (Main OSC Reg) */
#define CKGR_MOSCEN		((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
#define CKGR_OSCOUNT	((unsigned int) 0x08 <<  8) // (CKGR) Main Oscillator Start-u  
#define PMC_CSS_MAIN_CLK	((unsigned int) 0x1) 	// (PMC) Main Clock
#define PMC_CSS_PLLA_CLK    ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected
#define PMC_PRES_CLK        ((unsigned int) 0x0 << 2) //(PMC) Selected clock
#define PMC_MDIV_2          ((unsigned int) 0x1 << 8) //(PMC) The processor clk is twice as fast as the master clock
#define PMC_LOCKA       ((unsigned int) 0x1 <<  1) // (PMC) PLL A 
#define PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) Master Clock 

/* NAND FLASH Commands */
#define NAND_CMD_READ0		0x00
#define NAND_CMD_READ1		0x01
#define NAND_CMD_READ2		  0x50
#define NAND_CMD_READID		0x90
#define NAND_CMD_SEQIN		0x80
#define NAND_CMD_PAGEPROG	0x10
#define NAND_CMD_BLKERASE	0x60
#define NAND_CMD_BLKERASE_CONFIRM	0xD0
#define NAND_CMD_STATUSREG	0x70

/* SDRAM */
#define SDRAMC_NC_9			((unsigned int) 0x1) // No. of Column 9 bits
#define SDRAMC_NR_13		((unsigned int) 0x2 <<  2) // No. of Row 13 bits
#define SDRAMC_NB_4_BANKS   ((unsigned int) 0x1 <<  4) //  4 Banks
#define	SDRAMC_CAS_3        ((unsigned int) 0x3 <<  5) // CAS latency 3 cycles 
#define SDRAMC_DBW_32_BITS  ((unsigned int) 0x0 <<  7) // 32 Bits data bus
#define SDRAMC_TWR_2        ((unsigned int) 0x2 <<  8) // Write recovery time cycles  2
#define SDRAMC_TRC_7        ((unsigned int) 0x7 << 12) // RAS cycle time cycles  7
#define SDRAMC_TRP_2        ((unsigned int) 0x2 << 16) // RAS precharge time cycles  2  
#define SDRAMC_TRCD_2       ((unsigned int) 0x2 << 20) // Row to Column delay  2
#define SDRAMC_TRAS_5       ((unsigned int) 0x5 << 24) // Active to Precharg command Delay  5
#define SDRAMC_TXSR_8       ((unsigned int) 0x8 << 28) // Command Recovary Time Cycle  8
#define SDRAMC_MODE_RFSH_CMD	((unsigned int) 0x4) // Issue a Refresh
#define SDRAMC_MODE_LMR_CMD     ((unsigned int) 0x3) // Issue a Load Mode Register at every access
#define SDRAMC_MODE_NORMAL_CMD  ((unsigned int) 0x0) //  Normal Mode

//* DBGU *
#define DBGU_CR                (volatile unsigned int *)0xFFFFEE00
#define DBGU_MR                (volatile unsigned int *)0xFFFFEE04
#define DBGU_SR                (volatile unsigned int *)0xFFFFEE14
#define DBGU_RHR               (volatile unsigned int *)0xFFFFEE18
#define DBGU_THR               (volatile unsigned int *)0xFFFFEE1C
#define DBGU_BRGR              (volatile unsigned int *)0xFFFFEE20

// ========== Register definition for TWI peripheral ==========
#define TWI_THR             (volatile unsigned int *)0xFFF88034 // (TWI) Transmit Holding Register
#define TWI_IMR             (volatile unsigned int *)0xFFF8802C // (TWI) Interrupt Mask Register
#define TWI_IER             (volatile unsigned int *)0xFFF88024 // (TWI) Interrupt Enable Register
#define TWI_IADR            (volatile unsigned int *)0xFFF8800C // (TWI) Internal Address Register
#define TWI_MMR             (volatile unsigned int *)0xFFF88004 // (TWI) Master Mode Register
#define TWI_RHR             (volatile unsigned int *)0xFFF88030 // (TWI) Receive Holding Register
#define TWI_IDR             (volatile unsigned int *)0xFFF88028 // (TWI) Interrupt Disable Register
#define TWI_SR              (volatile unsigned int *)0xFFF88020 // (TWI) Status Register
#define TWI_CWGR            (volatile unsigned int *)0xFFF88010 // (TWI) Clock Waveform Generator Register
#define TWI_CR              (volatile unsigned int *)0xFFF88000 // (TWI) Control Register
#define TWI_SMR	          (volatile unsigned int *)0xFFF88008