fulladder1.v

来自「实现17位加法」· Verilog 代码 · 共 24 行

module fulladder1(sum,cout,cint,A,B);
input A,B;
input cint;
output sum;
output cout;


reg sum;
reg cout;
reg G;
reg P;




always@(A or B or cint)
 begin
  G<=A&B;
  P<=A+B;
  sum<=A^B^cint;
  cout<=(A&B)+(B&cint)+(A&cint);
  end

endmodule