adder17.v

来自「实现17位加法」· Verilog 代码 · 共 23 行

module adder17(X,Y,Cin,Cout,Sum);
 input[16:0] X,Y;
 input Cin;
 output[16:0] Sum;
 output Cout;
 
 wire [15:0]A,B; 
 wire [15:0]ESum;
 wire wire1;
 
 assign A=X[15:0];
 assign B=Y[15:0]; 
 
 
 //***Call a 16-bit CLA, and a one-bit full adder 17 constitute an adder***
 adder16  EX(.A(A),.B(B),.Cin(Cin),.Cout(wire1),.Sum(ESum));
 fulladder1 EU(.sum(Sum[16]),.cout(Cout),.cint(wire1),.A(X[16]),.B(Y[16]));
 
 assign Sum[15:0]=ESum;

 
 endmodule