adder17_tb.v

来自「实现17位加法」· Verilog 代码 · 共 27 行

module adder17_tb  ; 
 
  reg  [16:0]  X   ; 
  wire  [16:0]  Sum   ; 
  reg  [16:0]  Y   ; 
  reg    Cin   ; 
  wire    Cout   ; 
  
  
  initial 
    begin
    #0 X<=17'b11111000000000001;
       Y<=17'b01000000000000000;
       Cin<=0;
    #1000 $stop;
   end
  adder17  
   DUT  ( 
       .X (X ) ,
      .Sum (Sum ) ,
      .Y (Y ) ,
      .Cin (Cin ) ,
      .Cout (Cout ) ); 

endmodule