adder4.v

来自「实现17位加法」· Verilog 代码 · 共 24 行

module adder4(A[0],A[1],A[2],A[3],B[0],B[1],B[2],B[3],Cin,Cout,Sum[0],Sum[1],Sum[2],Sum[3],P[0],P[1],P[2],P[3],G[0],G[1],G[2],G[3]);
    input [3:0]A,B;
    input Cin;
    output [3:0]Sum;
    output [3:0]P,G;
    output Cout;
    
    wire[3:0]Sum;
    wire Cout;
    wire[3:0]P,G;
    wire C0,C1,C2;
    
    assign G=A&B;
    assign P=A^B;
    assign C0=G[0]|(P[0]&Cin);
    assign C1=G[1]|(G[0]&P[1])|(P[1]&P[0]&Cin);
    assign C2=G[2]|(G[1]&P[2])|(G[0]&P[2]&P[1])|(P[2]&P[1]&P[0]&Cin);
    assign Cout=G[3]|(G[2]&P[3])|(G[1]&P[3]&P[2])|(G[0]&P[3]&P[2]&P[1])|(P[3]&P[2]&P[1]&P[0]&Cin);
    assign Sum[0]=A[0]^B[0]^Cin;
    assign Sum[1]=A[1]^B[1]^C0;
    assign Sum[2]=A[2]^B[2]^C1;
    assign Sum[3]=A[3]^B[3]^C2;
endmodule