sender.v

自己写一个关于维mesh结构的noc网络

module sender(clk, send, req_out, dout, ack_in);
    input clk, send, ack_in;
    output [33:0] dout;
    output req_out;
    
    parameter IDLE = 0, SEND_HEAD = 1, SEND_TAIL = 2, WAIT_ACK_HEAD = 3, WAIT_ACK_TAIL = 4, WAIT_ACKH_DOWN = 5,
              WAIT_ACKT_DOWN = 6;
    reg [2:0] state;
    reg [33:0] dout_r;
    reg req_r;
    
    assign dout = dout_r;
    assign req_out = req_r;
    
    initial
    begin
        state = IDLE;
        dout_r = 0;
        req_r = 0;
    end
    
    always @(posedge clk)
    begin
        case(state)
            IDLE:
               begin
                   if(send == 1)
                   begin                                               
                     state <= SEND_HEAD;
                   end
               end
            SEND_HEAD:
            begin                
                req_r <= 1;
                dout_r <= 34'b1000000000000000000000000000000010;
                state <= WAIT_ACK_HEAD;
            end
            WAIT_ACK_HEAD:
            begin
                if(ack_in == 1)
                begin
                    req_r <= 0;
                    dout_r <= 0;
                    state <= WAIT_ACKH_DOWN;                    
                end
            end
            WAIT_ACKH_DOWN:
            begin
                if(ack_in == 0)
                state <= SEND_TAIL;
            end
            SEND_TAIL:
            begin
                req_r <= 1;
                dout_r <= 34'b0100001000010001000010000000000010;
                state <= WAIT_ACK_TAIL;
            end
            WAIT_ACK_TAIL:
            begin
                if(ack_in == 1)
                begin
                    req_r <= 0;
                    dout_r <= 0;
                    state <= WAIT_ACKT_DOWN;                    
                end
            end
            WAIT_ACKT_DOWN:
            begin
                if(ack_in == 0)
                state <= SEND_HEAD;
            end
        endcase
    end
endmodule

module receiver(clk, req_in, ack_out);
    input clk, req_in;
    output ack_out;
    reg ack;
    
    assign ack_out = ack;
    
    always @(posedge clk)
    begin
        if(req_in == 1)
          ack = 1;
        else
           ack = 0;
    end
endmodule