router_my_fifo.v

自己写的一个片上网络路由节点的fifo模块

// ****************************************//
// ****************************************//
// ****** THE ROUTER BASED ON MESH ********// 
// ******    ROUTER VERSION 1.0   *********//
// ******   CODING BY BAYINDALA   *********//
// ******       2008.10.18        *********//
// ****************************************//
// ****************************************//

//file name:router_fifo.v//

//`include "const_define.v"
//this the fifo module//
module module_fifo
(		clk,
		rst,
		data_in,
		write,
		read,
		data_out,
		empty,
		ack_out
);
parameter DATA=32,CTRL=4;	 
input	 clk;         			 	 //clk signal
input	 rst;       				 //rst signal
input	 [DATA+CTRL-1:0] data_in;    //input port


input	 read;    		   	 		 //read
input	 write;      			 	 //write

output 	 [DATA+CTRL-1:0] data_out;   //output port
output	 empty; 				 	 //show store memory empty_reg flag
//output	 full;  				 	 //show store memory full flag
output 	 ack_out;


parameter DEPTH=4,MAX_COUNT=2'b11;
wire [DATA+CTRL-1:0] data_out;
//reg		[DATA+CTRL-1:0] data_out_reg;

//assign data_out=data_out_reg;
wire empty;
reg 	empty_reg;
assign empty=empty_reg;
reg 	full;
    
reg		[DEPTH-1:0] tail;         //read pointer
reg		[DEPTH-1:0] head;         //write pointer
reg		[DEPTH-1:0] count;        //counter
reg		[DATA+CTRL-1:0] fifomem[0:MAX_COUNT];  //store unit 
wire    ack_out;
reg     ack_out_reg;
assign ack_out = ack_out_reg;
assign data_out = fifomem[tail];
    

//read date from fifo//
always@(posedge clk)
    begin
           if(rst==1)               //reset
           begin
               //data_out_reg<={(DATA+CTRL-1){1'b0}};
           end
          else if(read==1'b1&&empty_reg==1'b0)  //read valid and store memory is
          //else if(empty_reg==1'b0)            //                      not empty_reg, read out the fifo date*/                                                                   
           begin
               //data_out_reg<=fifomem[tail];
                 if(tail!=2'b11)
                  tail<=tail+1;
                  else
                  tail<=2'b00;
           end
    end
       
//write date to the fifo//
always @(posedge clk)
    begin
           if(rst==1'b0&&write==1'b1&&full==1'b0)
           /*write signal valid and store memory is not full, 
           write the date to fifo*/
           begin
               fifomem[head]<=data_in;
               if(head!=2'b11)
                  head<=head+1;
                  else
                  head<=2'b00;
           end
    end
       
       
//renew head pointer
always@(posedge clk)
    begin
       if(rst==1'b1)    //reset valid ,set head to zero
       begin
       head<=2'b00;
   	   end
       
       else
       begin
           if(write==1'b1&&full==1'b0)  //at write date status
           begin
              // head<=head+1;              //head pointer increase one
			   ack_out_reg=1'b1;
           end
		   else
			   ack_out_reg=1'b0;
       end
    end

//renew tail pointer
always@(posedge clk)
   begin
       if(rst==1'b1)           //reset valid ,set tail pointer to zero
       begin
           tail<=2'b00;
       end
//      /* else
//       begin
//           if(read==1'b1&&empty_reg==1'b0)    //at read date status
 //          begin
  //             tail<=tail+1;               //tail pointer increase one
 //          end
 //      end*/
   end
   
   
//renew counter
always@(posedge clk)
   begin
       if(rst==1'b1)         //reset signal valid ,set counter to 0
       begin
           count<=2'b00;
       end
       else
       begin
           case({read,write})
               2'b0:               //no read,no write
               count<=count;
               
               2'b01:               //write pointer
               if(count!=MAX_COUNT+1)//counter is not reach max of store 
                                       //unit,increase one
               count<=count+1;
               
               2'b10:               //read pointer
               if(count!=2'b00)
               count<=count-1;
               
               2'b11:            //write and read  at same time.
               if(empty_reg)
               begin
                  count<=count+1;
               end
               else
               begin
                 count<=count;    //counter does not change
               end
       	  endcase
   	   end
   end
   
   
//renew empty_reg flag bit
always @(count)
   begin
       if(count==2'b00)
       empty_reg<=1'b1;
       else
       empty_reg<=1'b0;
   end
   
   
//renew full flag bit
always@(count)
   begin
       if(count==MAX_COUNT+1)
       full<=1'b1;
       else
       full<=1'b0;
   end
endmodule //the end of module_fifo