📄 moter.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register timer:inst\|TCNT2\[6\] register timer:inst\|TCNT2\[15\] 147.41 MHz 6.784 ns Internal " "Info: Clock \"clk\" has Internal fmax of 147.41 MHz between source register \"timer:inst\|TCNT2\[6\]\" and destination register \"timer:inst\|TCNT2\[15\]\" (period= 6.784 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.520 ns + Longest register register " "Info: + Longest register to register delay is 6.520 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns timer:inst\|TCNT2\[6\] 1 REG LCFF_X21_Y4_N13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y4_N13; Fanout = 4; REG Node = 'timer:inst\|TCNT2\[6\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { timer:inst|TCNT2[6] } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.112 ns) + CELL(0.529 ns) 1.641 ns timer:inst\|Equal7~160 2 COMB LCCOMB_X22_Y4_N28 1 " "Info: 2: + IC(1.112 ns) + CELL(0.529 ns) = 1.641 ns; Loc. = LCCOMB_X22_Y4_N28; Fanout = 1; COMB Node = 'timer:inst\|Equal7~160'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.641 ns" { timer:inst|TCNT2[6] timer:inst|Equal7~160 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 143 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.103 ns) + CELL(0.589 ns) 3.333 ns timer:inst\|Equal7~162 3 COMB LCCOMB_X21_Y6_N0 2 " "Info: 3: + IC(1.103 ns) + CELL(0.589 ns) = 3.333 ns; Loc. = LCCOMB_X21_Y6_N0; Fanout = 2; COMB Node = 'timer:inst\|Equal7~162'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.692 ns" { timer:inst|Equal7~160 timer:inst|Equal7~162 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 143 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.104 ns) + CELL(0.206 ns) 4.643 ns timer:inst\|TCNT2\[9\]~759 4 COMB LCCOMB_X21_Y8_N20 16 " "Info: 4: + IC(1.104 ns) + CELL(0.206 ns) = 4.643 ns; Loc. = LCCOMB_X21_Y8_N20; Fanout = 16; COMB Node = 'timer:inst\|TCNT2\[9\]~759'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.310 ns" { timer:inst|Equal7~162 timer:inst|TCNT2[9]~759 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.055 ns) + CELL(0.822 ns) 6.520 ns timer:inst\|TCNT2\[15\] 5 REG LCFF_X21_Y4_N31 3 " "Info: 5: + IC(1.055 ns) + CELL(0.822 ns) = 6.520 ns; Loc. = LCFF_X21_Y4_N31; Fanout = 3; REG Node = 'timer:inst\|TCNT2\[15\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.877 ns" { timer:inst|TCNT2[9]~759 timer:inst|TCNT2[15] } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.146 ns ( 32.91 % ) " "Info: Total cell delay = 2.146 ns ( 32.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.374 ns ( 67.09 % ) " "Info: Total interconnect delay = 4.374 ns ( 67.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.520 ns" { timer:inst|TCNT2[6] timer:inst|Equal7~160 timer:inst|Equal7~162 timer:inst|TCNT2[9]~759 timer:inst|TCNT2[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.520 ns" { timer:inst|TCNT2[6] {} timer:inst|Equal7~160 {} timer:inst|Equal7~162 {} timer:inst|TCNT2[9]~759 {} timer:inst|TCNT2[15] {} } { 0.000ns 1.112ns 1.103ns 1.104ns 1.055ns } { 0.000ns 0.529ns 0.589ns 0.206ns 0.822ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.788 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 201 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 201; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.788 ns timer:inst\|TCNT2\[15\] 3 REG LCFF_X21_Y4_N31 3 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X21_Y4_N31; Fanout = 3; REG Node = 'timer:inst\|TCNT2\[15\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { clk~clkctrl timer:inst|TCNT2[15] } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.78 % ) " "Info: Total cell delay = 1.806 ns ( 64.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.22 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|TCNT2[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|TCNT2[15] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.788 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 201 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 201; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.788 ns timer:inst\|TCNT2\[6\] 3 REG LCFF_X21_Y4_N13 4 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X21_Y4_N13; Fanout = 4; REG Node = 'timer:inst\|TCNT2\[6\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { clk~clkctrl timer:inst|TCNT2[6] } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.78 % ) " "Info: Total cell delay = 1.806 ns ( 64.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.22 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|TCNT2[6] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|TCNT2[6] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|TCNT2[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|TCNT2[15] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|TCNT2[6] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|TCNT2[6] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.520 ns" { timer:inst|TCNT2[6] timer:inst|Equal7~160 timer:inst|Equal7~162 timer:inst|TCNT2[9]~759 timer:inst|TCNT2[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.520 ns" { timer:inst|TCNT2[6] {} timer:inst|Equal7~160 {} timer:inst|Equal7~162 {} timer:inst|TCNT2[9]~759 {} timer:inst|TCNT2[15] {} } { 0.000ns 1.112ns 1.103ns 1.104ns 1.055ns } { 0.000ns 0.529ns 0.589ns 0.206ns 0.822ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|TCNT2[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|TCNT2[15] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|TCNT2[6] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|TCNT2[6] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "timer:inst\|data\[14\]~reg0 addr\[5\] clk 15.289 ns register " "Info: tsu for register \"timer:inst\|data\[14\]~reg0\" (data pin = \"addr\[5\]\", clock pin = \"clk\") is 15.289 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.107 ns + Longest pin register " "Info: + Longest pin to register delay is 18.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.964 ns) 0.964 ns addr\[5\] 1 PIN PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.964 ns) = 0.964 ns; Loc. = PIN_86; Fanout = 1; PIN Node = 'addr\[5\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr[5] } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 640 32 200 656 "addr\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.751 ns) + CELL(0.534 ns) 7.249 ns timer:inst\|Equal0~59 2 COMB LCCOMB_X19_Y2_N20 3 " "Info: 2: + IC(5.751 ns) + CELL(0.534 ns) = 7.249 ns; Loc. = LCCOMB_X19_Y2_N20; Fanout = 3; COMB Node = 'timer:inst\|Equal0~59'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.285 ns" { addr[5] timer:inst|Equal0~59 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.858 ns) + CELL(0.606 ns) 9.713 ns timer:inst\|Equal2~52 3 COMB LCCOMB_X24_Y6_N12 5 " "Info: 3: + IC(1.858 ns) + CELL(0.606 ns) = 9.713 ns; Loc. = LCCOMB_X24_Y6_N12; Fanout = 5; COMB Node = 'timer:inst\|Equal2~52'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.464 ns" { timer:inst|Equal0~59 timer:inst|Equal2~52 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.572 ns) + CELL(0.206 ns) 11.491 ns timer:inst\|data\[15\]~1681 4 COMB LCCOMB_X20_Y9_N28 24 " "Info: 4: + IC(1.572 ns) + CELL(0.206 ns) = 11.491 ns; Loc. = LCCOMB_X20_Y9_N28; Fanout = 24; COMB Node = 'timer:inst\|data\[15\]~1681'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.778 ns" { timer:inst|Equal2~52 timer:inst|data[15]~1681 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.456 ns) + CELL(0.650 ns) 14.597 ns timer:inst\|data\[14\]~1651 5 COMB LCCOMB_X24_Y5_N30 1 " "Info: 5: + IC(2.456 ns) + CELL(0.650 ns) = 14.597 ns; Loc. = LCCOMB_X24_Y5_N30; Fanout = 1; COMB Node = 'timer:inst\|data\[14\]~1651'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.106 ns" { timer:inst|data[15]~1681 timer:inst|data[14]~1651 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.469 ns) + CELL(0.206 ns) 16.272 ns timer:inst\|data\[14\]~1652 6 COMB LCCOMB_X20_Y7_N2 1 " "Info: 6: + IC(1.469 ns) + CELL(0.206 ns) = 16.272 ns; Loc. = LCCOMB_X20_Y7_N2; Fanout = 1; COMB Node = 'timer:inst\|data\[14\]~1652'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.675 ns" { timer:inst|data[14]~1651 timer:inst|data[14]~1652 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.076 ns) + CELL(0.651 ns) 17.999 ns timer:inst\|data\[14\]~1519 7 COMB LCCOMB_X24_Y7_N10 1 " "Info: 7: + IC(1.076 ns) + CELL(0.651 ns) = 17.999 ns; Loc. = LCCOMB_X24_Y7_N10; Fanout = 1; COMB Node = 'timer:inst\|data\[14\]~1519'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.727 ns" { timer:inst|data[14]~1652 timer:inst|data[14]~1519 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 18.107 ns timer:inst\|data\[14\]~reg0 8 REG LCFF_X24_Y7_N11 1 " "Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 18.107 ns; Loc. = LCFF_X24_Y7_N11; Fanout = 1; REG Node = 'timer:inst\|data\[14\]~reg0'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { timer:inst|data[14]~1519 timer:inst|data[14]~reg0 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.925 ns ( 21.68 % ) " "Info: Total cell delay = 3.925 ns ( 21.68 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.182 ns ( 78.32 % ) " "Info: Total interconnect delay = 14.182 ns ( 78.32 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "18.107 ns" { addr[5] timer:inst|Equal0~59 timer:inst|Equal2~52 timer:inst|data[15]~1681 timer:inst|data[14]~1651 timer:inst|data[14]~1652 timer:inst|data[14]~1519 timer:inst|data[14]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "18.107 ns" { addr[5] {} addr[5]~combout {} timer:inst|Equal0~59 {} timer:inst|Equal2~52 {} timer:inst|data[15]~1681 {} timer:inst|data[14]~1651 {} timer:inst|data[14]~1652 {} timer:inst|data[14]~1519 {} timer:inst|data[14]~reg0 {} } { 0.000ns 0.000ns 5.751ns 1.858ns 1.572ns 2.456ns 1.469ns 1.076ns 0.000ns } { 0.000ns 0.964ns 0.534ns 0.606ns 0.206ns 0.650ns 0.206ns 0.651ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.778 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 201 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 201; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.666 ns) 2.778 ns timer:inst\|data\[14\]~reg0 3 REG LCFF_X24_Y7_N11 1 " "Info: 3: + IC(0.829 ns) + CELL(0.666 ns) = 2.778 ns; Loc. = LCFF_X24_Y7_N11; Fanout = 1; REG Node = 'timer:inst\|data\[14\]~reg0'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk~clkctrl timer:inst|data[14]~reg0 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.01 % ) " "Info: Total cell delay = 1.806 ns ( 65.01 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.972 ns ( 34.99 % ) " "Info: Total interconnect delay = 0.972 ns ( 34.99 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.778 ns" { clk clk~clkctrl timer:inst|data[14]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.778 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|data[14]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.829ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "18.107 ns" { addr[5] timer:inst|Equal0~59 timer:inst|Equal2~52 timer:inst|data[15]~1681 timer:inst|data[14]~1651 timer:inst|data[14]~1652 timer:inst|data[14]~1519 timer:inst|data[14]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "18.107 ns" { addr[5] {} addr[5]~combout {} timer:inst|Equal0~59 {} timer:inst|Equal2~52 {} timer:inst|data[15]~1681 {} timer:inst|data[14]~1651 {} timer:inst|data[14]~1652 {} timer:inst|data[14]~1519 {} timer:inst|data[14]~reg0 {} } { 0.000ns 0.000ns 5.751ns 1.858ns 1.572ns 2.456ns 1.469ns 1.076ns 0.000ns } { 0.000ns 0.964ns 0.534ns 0.606ns 0.206ns 0.650ns 0.206ns 0.651ns 0.108ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.778 ns" { clk clk~clkctrl timer:inst|data[14]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.778 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|data[14]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.829ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[6\] timer:inst\|data\[0\]~en 8.949 ns register " "Info: tco from clock \"clk\" to destination pin \"data\[6\]\" through register \"timer:inst\|data\[0\]~en\" is 8.949 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.788 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 201 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 201; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.788 ns timer:inst\|data\[0\]~en 3 REG LCFF_X21_Y8_N7 16 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X21_Y8_N7; Fanout = 16; REG Node = 'timer:inst\|data\[0\]~en'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { clk~clkctrl timer:inst|data[0]~en } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.78 % ) " "Info: Total cell delay = 1.806 ns ( 64.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.22 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|data[0]~en } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|data[0]~en {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.857 ns + Longest register pin " "Info: + Longest register to pin delay is 5.857 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns timer:inst\|data\[0\]~en 1 REG LCFF_X21_Y8_N7 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N7; Fanout = 16; REG Node = 'timer:inst\|data\[0\]~en'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { timer:inst|data[0]~en } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.489 ns) + CELL(3.368 ns) 5.857 ns data\[6\] 2 PIN PIN_96 0 " "Info: 2: + IC(2.489 ns) + CELL(3.368 ns) = 5.857 ns; Loc. = PIN_96; Fanout = 0; PIN Node = 'data\[6\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.857 ns" { timer:inst|data[0]~en data[6] } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 560 480 656 576 "data\[15..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.368 ns ( 57.50 % ) " "Info: Total cell delay = 3.368 ns ( 57.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.489 ns ( 42.50 % ) " "Info: Total interconnect delay = 2.489 ns ( 42.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.857 ns" { timer:inst|data[0]~en data[6] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.857 ns" { timer:inst|data[0]~en {} data[6] {} } { 0.000ns 2.489ns } { 0.000ns 3.368ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|data[0]~en } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|data[0]~en {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.857 ns" { timer:inst|data[0]~en data[6] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.857 ns" { timer:inst|data[0]~en {} data[6] {} } { 0.000ns 2.489ns } { 0.000ns 3.368ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "timer:inst\|data\[1\]~reg0 rst clk -0.821 ns register " "Info: th for register \"timer:inst\|data\[1\]~reg0\" (data pin = \"rst\", clock pin = \"clk\") is -0.821 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.774 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 201 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 201; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.825 ns) + CELL(0.666 ns) 2.774 ns timer:inst\|data\[1\]~reg0 3 REG LCFF_X21_Y7_N11 1 " "Info: 3: + IC(0.825 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X21_Y7_N11; Fanout = 1; REG Node = 'timer:inst\|data\[1\]~reg0'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.491 ns" { clk~clkctrl timer:inst|data[1]~reg0 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.10 % ) " "Info: Total cell delay = 1.806 ns ( 65.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.968 ns ( 34.90 % ) " "Info: Total interconnect delay = 0.968 ns ( 34.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl timer:inst|data[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|data[1]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.825ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.901 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.901 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns rst 1 PIN PIN_24 26 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 26; PIN Node = 'rst'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 560 32 200 576 "rst" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.916 ns) + CELL(0.855 ns) 3.901 ns timer:inst\|data\[1\]~reg0 2 REG LCFF_X21_Y7_N11 1 " "Info: 2: + IC(1.916 ns) + CELL(0.855 ns) = 3.901 ns; Loc. = LCFF_X21_Y7_N11; Fanout = 1; REG Node = 'timer:inst\|data\[1\]~reg0'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.771 ns" { rst timer:inst|data[1]~reg0 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.985 ns ( 50.88 % ) " "Info: Total cell delay = 1.985 ns ( 50.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.916 ns ( 49.12 % ) " "Info: Total interconnect delay = 1.916 ns ( 49.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.901 ns" { rst timer:inst|data[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.901 ns" { rst {} rst~combout {} timer:inst|data[1]~reg0 {} } { 0.000ns 0.000ns 1.916ns } { 0.000ns 1.130ns 0.855ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl timer:inst|data[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|data[1]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.825ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.901 ns" { rst timer:inst|data[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.901 ns" { rst {} rst~combout {} timer:inst|data[1]~reg0 {} } { 0.000ns 0.000ns 1.916ns } { 0.000ns 1.130ns 0.855ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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