prev_cmp_moter.fit.qmsg

一个基于vhdl语言的脉冲宽度调制。并且有两个脉冲输出

{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 30 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  30 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 35 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  35 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 36 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  36 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  36 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.050 ns register register " "Info: Estimated most critical path is register to register delay of 6.050 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns timer:inst\|TCMP2\[0\] 1 REG LAB_X21_Y11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y11; Fanout = 1; REG Node = 'timer:inst\|TCMP2\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { timer:inst|TCMP2[0] } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.356 ns) + CELL(0.621 ns) 1.977 ns timer:inst\|LessThan3~209 2 COMB LAB_X25_Y11 1 " "Info: 2: + IC(1.356 ns) + CELL(0.621 ns) = 1.977 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~209'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.977 ns" { timer:inst|TCMP2[0] timer:inst|LessThan3~209 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.063 ns timer:inst\|LessThan3~211 3 COMB LAB_X25_Y11 1 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 2.063 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~211'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~209 timer:inst|LessThan3~211 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.149 ns timer:inst\|LessThan3~213 4 COMB LAB_X25_Y11 1 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 2.149 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~213'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~211 timer:inst|LessThan3~213 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.235 ns timer:inst\|LessThan3~215 5 COMB LAB_X25_Y11 1 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 2.235 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~215'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~213 timer:inst|LessThan3~215 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.321 ns timer:inst\|LessThan3~217 6 COMB LAB_X25_Y11 1 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 2.321 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~217'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~215 timer:inst|LessThan3~217 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.407 ns timer:inst\|LessThan3~219 7 COMB LAB_X25_Y11 1 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 2.407 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~219'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~217 timer:inst|LessThan3~219 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.493 ns timer:inst\|LessThan3~221 8 COMB LAB_X25_Y11 1 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 2.493 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~221'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~219 timer:inst|LessThan3~221 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.579 ns timer:inst\|LessThan3~223 9 COMB LAB_X25_Y11 1 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.579 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~223'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~221 timer:inst|LessThan3~223 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.665 ns timer:inst\|LessThan3~225 10 COMB LAB_X25_Y11 1 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.665 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~225'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~223 timer:inst|LessThan3~225 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.751 ns timer:inst\|LessThan3~227 11 COMB LAB_X25_Y11 1 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.751 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~227'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~225 timer:inst|LessThan3~227 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.837 ns timer:inst\|LessThan3~229 12 COMB LAB_X25_Y11 1 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.837 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~229'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~227 timer:inst|LessThan3~229 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.923 ns timer:inst\|LessThan3~231 13 COMB LAB_X25_Y11 1 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.923 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~231'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~229 timer:inst|LessThan3~231 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.009 ns timer:inst\|LessThan3~233 14 COMB LAB_X25_Y11 1 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 3.009 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~233'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~231 timer:inst|LessThan3~233 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.095 ns timer:inst\|LessThan3~235 15 COMB LAB_X25_Y11 1 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 3.095 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~235'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~233 timer:inst|LessThan3~235 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.181 ns timer:inst\|LessThan3~237 16 COMB LAB_X25_Y11 1 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 3.181 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~237'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { timer:inst|LessThan3~235 timer:inst|LessThan3~237 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 3.687 ns timer:inst\|LessThan3~238 17 COMB LAB_X25_Y11 1 " "Info: 17: + IC(0.000 ns) + CELL(0.506 ns) = 3.687 ns; Loc. = LAB_X25_Y11; Fanout = 1; COMB Node = 'timer:inst\|LessThan3~238'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { timer:inst|LessThan3~237 timer:inst|LessThan3~238 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.605 ns) + CELL(0.650 ns) 5.942 ns timer:inst\|pwmout2~18 18 COMB LAB_X15_Y11 1 " "Info: 18: + IC(1.605 ns) + CELL(0.650 ns) = 5.942 ns; Loc. = LAB_X15_Y11; Fanout = 1; COMB Node = 'timer:inst\|pwmout2~18'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.255 ns" { timer:inst|LessThan3~238 timer:inst|pwmout2~18 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.050 ns timer:inst\|pwmout2 19 REG LAB_X15_Y11 18 " "Info: 19: + IC(0.000 ns) + CELL(0.108 ns) = 6.050 ns; Loc. = LAB_X15_Y11; Fanout = 18; REG Node = 'timer:inst\|pwmout2'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { timer:inst|pwmout2~18 timer:inst|pwmout2 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.089 ns ( 51.06 % ) " "Info: Total cell delay = 3.089 ns ( 51.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.961 ns ( 48.94 % ) " "Info: Total interconnect delay = 2.961 ns ( 48.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.050 ns" { timer:inst|TCMP2[0] timer:inst|LessThan3~209 timer:inst|LessThan3~211 timer:inst|LessThan3~213 timer:inst|LessThan3~215 timer:inst|LessThan3~217 timer:inst|LessThan3~219 timer:inst|LessThan3~221 timer:inst|LessThan3~223 timer:inst|LessThan3~225 timer:inst|LessThan3~227 timer:inst|LessThan3~229 timer:inst|LessThan3~231 timer:inst|LessThan3~233 timer:inst|LessThan3~235 timer:inst|LessThan3~237 timer:inst|LessThan3~238 timer:inst|pwmout2~18 timer:inst|pwmout2 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}