moter.map.qmsg

一个基于vhdl语言的脉冲宽度调制。并且有两个脉冲输出

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 19 23:54:00 2008 " "Info: Processing started: Fri Sep 19 23:54:00 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off moter -c moter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off moter -c moter" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "moter.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file moter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 moter " "Info: Found entity 1: moter" {  } { { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fredivn.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fredivn.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fredivn-behave " "Info: Found design unit 1: fredivn-behave" {  } { { "fredivn.vhd" "" { Text "E:/FPGA-job/moter/fredivn.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fredivn " "Info: Found entity 1: fredivn" {  } { { "fredivn.vhd" "" { Text "E:/FPGA-job/moter/fredivn.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file timer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 timer-behave " "Info: Found design unit 1: timer-behave" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 timer " "Info: Found entity 1: timer" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "moter " "Info: Elaborating entity \"moter\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer timer:inst " "Info: Elaborating entity \"timer\" for hierarchy \"timer:inst\"" {  } { { "moter.bdf" "inst" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 536 272 424 696 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[1\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[1\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[2\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[2\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[3\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[3\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[4\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[4\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[5\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[5\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[6\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[6\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[7\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[7\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[8\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[8\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[9\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[9\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[10\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[10\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[11\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[11\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[12\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[12\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[13\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[13\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[14\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[14\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "timer:inst\|data\[15\]~en timer:inst\|data\[0\]~en " "Info: Duplicate register \"timer:inst\|data\[15\]~en\" merged to single register \"timer:inst\|data\[0\]~en\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "376 " "Info: Implemented 376 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "343 " "Info: Implemented 343 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Allocated 162 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 19 23:54:10 2008 " "Info: Processing ended: Fri Sep 19 23:54:10 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}