📄 prev_cmp_moter.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register timer:inst\|TCNT1\[1\] register timer:inst\|TCNT1\[15\] 166.83 MHz 5.994 ns Internal " "Info: Clock \"clk\" has Internal fmax of 166.83 MHz between source register \"timer:inst\|TCNT1\[1\]\" and destination register \"timer:inst\|TCNT1\[15\]\" (period= 5.994 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.730 ns + Longest register register " "Info: + Longest register to register delay is 5.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns timer:inst\|TCNT1\[1\] 1 REG LCFF_X15_Y10_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y10_N3; Fanout = 4; REG Node = 'timer:inst\|TCNT1\[1\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { timer:inst|TCNT1[1] } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.465 ns) + CELL(0.370 ns) 1.835 ns timer:inst\|Equal6~161 2 COMB LCCOMB_X15_Y11_N16 1 " "Info: 2: + IC(1.465 ns) + CELL(0.370 ns) = 1.835 ns; Loc. = LCCOMB_X15_Y11_N16; Fanout = 1; COMB Node = 'timer:inst\|Equal6~161'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.835 ns" { timer:inst|TCNT1[1] timer:inst|Equal6~161 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 97 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.614 ns) 2.848 ns timer:inst\|Equal6~162 3 COMB LCCOMB_X15_Y11_N10 2 " "Info: 3: + IC(0.399 ns) + CELL(0.614 ns) = 2.848 ns; Loc. = LCCOMB_X15_Y11_N10; Fanout = 2; COMB Node = 'timer:inst\|Equal6~162'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.013 ns" { timer:inst|Equal6~161 timer:inst|Equal6~162 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 97 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.651 ns) 3.896 ns timer:inst\|TCNT1\[14\]~759 4 COMB LCCOMB_X15_Y11_N24 16 " "Info: 4: + IC(0.397 ns) + CELL(0.651 ns) = 3.896 ns; Loc. = LCCOMB_X15_Y11_N24; Fanout = 16; COMB Node = 'timer:inst\|TCNT1\[14\]~759'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.048 ns" { timer:inst|Equal6~162 timer:inst|TCNT1[14]~759 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.012 ns) + CELL(0.822 ns) 5.730 ns timer:inst\|TCNT1\[15\] 5 REG LCFF_X15_Y10_N31 3 " "Info: 5: + IC(1.012 ns) + CELL(0.822 ns) = 5.730 ns; Loc. = LCFF_X15_Y10_N31; Fanout = 3; REG Node = 'timer:inst\|TCNT1\[15\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.834 ns" { timer:inst|TCNT1[14]~759 timer:inst|TCNT1[15] } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.457 ns ( 42.88 % ) " "Info: Total cell delay = 2.457 ns ( 42.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.273 ns ( 57.12 % ) " "Info: Total interconnect delay = 3.273 ns ( 57.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.730 ns" { timer:inst|TCNT1[1] timer:inst|Equal6~161 timer:inst|Equal6~162 timer:inst|TCNT1[14]~759 timer:inst|TCNT1[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.730 ns" { timer:inst|TCNT1[1] {} timer:inst|Equal6~161 {} timer:inst|Equal6~162 {} timer:inst|TCNT1[14]~759 {} timer:inst|TCNT1[15] {} } { 0.000ns 1.465ns 0.399ns 0.397ns 1.012ns } { 0.000ns 0.370ns 0.614ns 0.651ns 0.822ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.788 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 201 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 201; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.788 ns timer:inst\|TCNT1\[15\] 3 REG LCFF_X15_Y10_N31 3 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X15_Y10_N31; Fanout = 3; REG Node = 'timer:inst\|TCNT1\[15\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { clk~clkctrl timer:inst|TCNT1[15] } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.78 % ) " "Info: Total cell delay = 1.806 ns ( 64.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.22 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|TCNT1[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|TCNT1[15] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.788 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 201 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 201; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.788 ns timer:inst\|TCNT1\[1\] 3 REG LCFF_X15_Y10_N3 4 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X15_Y10_N3; Fanout = 4; REG Node = 'timer:inst\|TCNT1\[1\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { clk~clkctrl timer:inst|TCNT1[1] } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.78 % ) " "Info: Total cell delay = 1.806 ns ( 64.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.22 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|TCNT1[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|TCNT1[1] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|TCNT1[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|TCNT1[15] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|TCNT1[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|TCNT1[1] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.730 ns" { timer:inst|TCNT1[1] timer:inst|Equal6~161 timer:inst|Equal6~162 timer:inst|TCNT1[14]~759 timer:inst|TCNT1[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.730 ns" { timer:inst|TCNT1[1] {} timer:inst|Equal6~161 {} timer:inst|Equal6~162 {} timer:inst|TCNT1[14]~759 {} timer:inst|TCNT1[15] {} } { 0.000ns 1.465ns 0.399ns 0.397ns 1.012ns } { 0.000ns 0.370ns 0.614ns 0.651ns 0.822ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|TCNT1[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|TCNT1[15] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl timer:inst|TCNT1[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|TCNT1[1] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "timer:inst\|data\[10\]~reg0 addr\[5\] clk 13.885 ns register " "Info: tsu for register \"timer:inst\|data\[10\]~reg0\" (data pin = \"addr\[5\]\", clock pin = \"clk\") is 13.885 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.712 ns + Longest pin register " "Info: + Longest pin to register delay is 16.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns addr\[5\] 1 PIN PIN_80 1 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_80; Fanout = 1; PIN Node = 'addr\[5\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr[5] } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 640 32 200 656 "addr\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.232 ns) + CELL(0.534 ns) 7.750 ns timer:inst\|Equal0~59 2 COMB LCCOMB_X18_Y8_N10 3 " "Info: 2: + IC(6.232 ns) + CELL(0.534 ns) = 7.750 ns; Loc. = LCCOMB_X18_Y8_N10; Fanout = 3; COMB Node = 'timer:inst\|Equal0~59'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.766 ns" { addr[5] timer:inst|Equal0~59 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.374 ns) + CELL(0.206 ns) 8.330 ns timer:inst\|Equal2~52 3 COMB LCCOMB_X18_Y8_N28 5 " "Info: 3: + IC(0.374 ns) + CELL(0.206 ns) = 8.330 ns; Loc. = LCCOMB_X18_Y8_N28; Fanout = 5; COMB Node = 'timer:inst\|Equal2~52'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.580 ns" { timer:inst|Equal0~59 timer:inst|Equal2~52 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.822 ns) + CELL(0.651 ns) 10.803 ns timer:inst\|data\[15\]~1681 4 COMB LCCOMB_X20_Y10_N0 24 " "Info: 4: + IC(1.822 ns) + CELL(0.651 ns) = 10.803 ns; Loc. = LCCOMB_X20_Y10_N0; Fanout = 24; COMB Node = 'timer:inst\|data\[15\]~1681'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.473 ns" { timer:inst|Equal2~52 timer:inst|data[15]~1681 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.877 ns) + CELL(0.624 ns) 13.304 ns timer:inst\|data\[10\]~1659 5 COMB LCCOMB_X21_Y8_N24 1 " "Info: 5: + IC(1.877 ns) + CELL(0.624 ns) = 13.304 ns; Loc. = LCCOMB_X21_Y8_N24; Fanout = 1; COMB Node = 'timer:inst\|data\[10\]~1659'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.501 ns" { timer:inst|data[15]~1681 timer:inst|data[10]~1659 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.088 ns) + CELL(0.206 ns) 14.598 ns timer:inst\|data\[10\]~1660 6 COMB LCCOMB_X21_Y11_N0 1 " "Info: 6: + IC(1.088 ns) + CELL(0.206 ns) = 14.598 ns; Loc. = LCCOMB_X21_Y11_N0; Fanout = 1; COMB Node = 'timer:inst\|data\[10\]~1660'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.294 ns" { timer:inst|data[10]~1659 timer:inst|data[10]~1660 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.206 ns) 16.604 ns timer:inst\|data\[10\]~1523 7 COMB LCCOMB_X20_Y8_N2 1 " "Info: 7: + IC(1.800 ns) + CELL(0.206 ns) = 16.604 ns; Loc. = LCCOMB_X20_Y8_N2; Fanout = 1; COMB Node = 'timer:inst\|data\[10\]~1523'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.006 ns" { timer:inst|data[10]~1660 timer:inst|data[10]~1523 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 16.712 ns timer:inst\|data\[10\]~reg0 8 REG LCFF_X20_Y8_N3 1 " "Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 16.712 ns; Loc. = LCFF_X20_Y8_N3; Fanout = 1; REG Node = 'timer:inst\|data\[10\]~reg0'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { timer:inst|data[10]~1523 timer:inst|data[10]~reg0 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.519 ns ( 21.06 % ) " "Info: Total cell delay = 3.519 ns ( 21.06 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.193 ns ( 78.94 % ) " "Info: Total interconnect delay = 13.193 ns ( 78.94 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.712 ns" { addr[5] timer:inst|Equal0~59 timer:inst|Equal2~52 timer:inst|data[15]~1681 timer:inst|data[10]~1659 timer:inst|data[10]~1660 timer:inst|data[10]~1523 timer:inst|data[10]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.712 ns" { addr[5] {} addr[5]~combout {} timer:inst|Equal0~59 {} timer:inst|Equal2~52 {} timer:inst|data[15]~1681 {} timer:inst|data[10]~1659 {} timer:inst|data[10]~1660 {} timer:inst|data[10]~1523 {} timer:inst|data[10]~reg0 {} } { 0.000ns 0.000ns 6.232ns 0.374ns 1.822ns 1.877ns 1.088ns 1.800ns 0.000ns } { 0.000ns 0.984ns 0.534ns 0.206ns 0.651ns 0.624ns 0.206ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.787 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 201 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 201; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.666 ns) 2.787 ns timer:inst\|data\[10\]~reg0 3 REG LCFF_X20_Y8_N3 1 " "Info: 3: + IC(0.838 ns) + CELL(0.666 ns) = 2.787 ns; Loc. = LCFF_X20_Y8_N3; Fanout = 1; REG Node = 'timer:inst\|data\[10\]~reg0'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { clk~clkctrl timer:inst|data[10]~reg0 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.80 % ) " "Info: Total cell delay = 1.806 ns ( 64.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns ( 35.20 % ) " "Info: Total interconnect delay = 0.981 ns ( 35.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { clk clk~clkctrl timer:inst|data[10]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|data[10]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.838ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.712 ns" { addr[5] timer:inst|Equal0~59 timer:inst|Equal2~52 timer:inst|data[15]~1681 timer:inst|data[10]~1659 timer:inst|data[10]~1660 timer:inst|data[10]~1523 timer:inst|data[10]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.712 ns" { addr[5] {} addr[5]~combout {} timer:inst|Equal0~59 {} timer:inst|Equal2~52 {} timer:inst|data[15]~1681 {} timer:inst|data[10]~1659 {} timer:inst|data[10]~1660 {} timer:inst|data[10]~1523 {} timer:inst|data[10]~reg0 {} } { 0.000ns 0.000ns 6.232ns 0.374ns 1.822ns 1.877ns 1.088ns 1.800ns 0.000ns } { 0.000ns 0.984ns 0.534ns 0.206ns 0.651ns 0.624ns 0.206ns 0.206ns 0.108ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { clk clk~clkctrl timer:inst|data[10]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|data[10]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.838ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data\[8\] timer:inst\|data\[0\]~en 8.898 ns register " "Info: tco from clock \"clk\" to destination pin \"data\[8\]\" through register \"timer:inst\|data\[0\]~en\" is 8.898 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.795 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.795 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 201 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 201; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.846 ns) + CELL(0.666 ns) 2.795 ns timer:inst\|data\[0\]~en 3 REG LCFF_X19_Y10_N23 16 " "Info: 3: + IC(0.846 ns) + CELL(0.666 ns) = 2.795 ns; Loc. = LCFF_X19_Y10_N23; Fanout = 16; REG Node = 'timer:inst\|data\[0\]~en'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.512 ns" { clk~clkctrl timer:inst|data[0]~en } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.62 % ) " "Info: Total cell delay = 1.806 ns ( 64.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 35.38 % ) " "Info: Total interconnect delay = 0.989 ns ( 35.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.795 ns" { clk clk~clkctrl timer:inst|data[0]~en } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.795 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|data[0]~en {} } { 0.000ns 0.000ns 0.143ns 0.846ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.799 ns + Longest register pin " "Info: + Longest register to pin delay is 5.799 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns timer:inst\|data\[0\]~en 1 REG LCFF_X19_Y10_N23 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y10_N23; Fanout = 16; REG Node = 'timer:inst\|data\[0\]~en'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { timer:inst|data[0]~en } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.461 ns) + CELL(3.338 ns) 5.799 ns data\[8\] 2 PIN PIN_84 0 " "Info: 2: + IC(2.461 ns) + CELL(3.338 ns) = 5.799 ns; Loc. = PIN_84; Fanout = 0; PIN Node = 'data\[8\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.799 ns" { timer:inst|data[0]~en data[8] } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 560 480 656 576 "data\[15..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.338 ns ( 57.56 % ) " "Info: Total cell delay = 3.338 ns ( 57.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.461 ns ( 42.44 % ) " "Info: Total interconnect delay = 2.461 ns ( 42.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.799 ns" { timer:inst|data[0]~en data[8] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.799 ns" { timer:inst|data[0]~en {} data[8] {} } { 0.000ns 2.461ns } { 0.000ns 3.338ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.795 ns" { clk clk~clkctrl timer:inst|data[0]~en } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.795 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|data[0]~en {} } { 0.000ns 0.000ns 0.143ns 0.846ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.799 ns" { timer:inst|data[0]~en data[8] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.799 ns" { timer:inst|data[0]~en {} data[8] {} } { 0.000ns 2.461ns } { 0.000ns 3.338ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "timer:inst\|data\[15\]~reg0 rst clk -0.455 ns register " "Info: th for register \"timer:inst\|data\[15\]~reg0\" (data pin = \"rst\", clock pin = \"clk\") is -0.455 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.787 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 201 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 201; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 576 32 200 592 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.666 ns) 2.787 ns timer:inst\|data\[15\]~reg0 3 REG LCFF_X20_Y8_N5 1 " "Info: 3: + IC(0.838 ns) + CELL(0.666 ns) = 2.787 ns; Loc. = LCFF_X20_Y8_N5; Fanout = 1; REG Node = 'timer:inst\|data\[15\]~reg0'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { clk~clkctrl timer:inst|data[15]~reg0 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.80 % ) " "Info: Total cell delay = 1.806 ns ( 64.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns ( 35.20 % ) " "Info: Total interconnect delay = 0.981 ns ( 35.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { clk clk~clkctrl timer:inst|data[15]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|data[15]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.838ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.548 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.548 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns rst 1 PIN PIN_24 26 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 26; PIN Node = 'rst'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { { 560 32 200 576 "rst" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.563 ns) + CELL(0.855 ns) 3.548 ns timer:inst\|data\[15\]~reg0 2 REG LCFF_X20_Y8_N5 1 " "Info: 2: + IC(1.563 ns) + CELL(0.855 ns) = 3.548 ns; Loc. = LCFF_X20_Y8_N5; Fanout = 1; REG Node = 'timer:inst\|data\[15\]~reg0'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.418 ns" { rst timer:inst|data[15]~reg0 } "NODE_NAME" } } { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 41 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.985 ns ( 55.95 % ) " "Info: Total cell delay = 1.985 ns ( 55.95 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.563 ns ( 44.05 % ) " "Info: Total interconnect delay = 1.563 ns ( 44.05 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.548 ns" { rst timer:inst|data[15]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.548 ns" { rst {} rst~combout {} timer:inst|data[15]~reg0 {} } { 0.000ns 0.000ns 1.563ns } { 0.000ns 1.130ns 0.855ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { clk clk~clkctrl timer:inst|data[15]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { clk {} clk~combout {} clk~clkctrl {} timer:inst|data[15]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.838ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.548 ns" { rst timer:inst|data[15]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.548 ns" { rst {} rst~combout {} timer:inst|data[15]~reg0 {} } { 0.000ns 0.000ns 1.563ns } { 0.000ns 1.130ns 0.855ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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