prev_cmp_moter.map.qmsg

一个基于vhdl语言的脉冲宽度调制。并且有两个脉冲输出

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 19 23:53:32 2008 " "Info: Processing started: Fri Sep 19 23:53:32 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off moter -c moter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off moter -c moter" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "moter.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file moter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 moter " "Info: Found entity 1: moter" {  } { { "moter.bdf" "" { Schematic "E:/FPGA-job/moter/moter.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fredivn.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fredivn.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fredivn-behave " "Info: Found design unit 1: fredivn-behave" {  } { { "fredivn.vhd" "" { Text "E:/FPGA-job/moter/fredivn.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fredivn " "Info: Found entity 1: fredivn" {  } { { "fredivn.vhd" "" { Text "E:/FPGA-job/moter/fredivn.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"out1\";  expecting \"then\" timer.vhd(124) " "Error (10500): VHDL syntax error at timer.vhd(124) near text \"out1\";  expecting \"then\"" {  } { { "timer.vhd" "" { Text "E:/FPGA-job/moter/timer.vhd" 124 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timer.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file timer.vhd" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "153 " "Info: Allocated 153 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Fri Sep 19 23:53:39 2008 " "Error: Processing ended: Fri Sep 19 23:53:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Error: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}