uart_controler_0622.v

自己设计的串口数据格式转换模块

//==============================================================================
//
//      GPRT, CFTC group, ICT of CAS
//      2007
//
//
//      (c) 2007, ICT of CAS. All rights reserved
//
//==============================================================================
//      CFTC group, ICT of CAS
//==============================================================================
//	Filename	:	uart_controler.v
//	Version		:	1.00
//	Date		:	2007-04-09
//	Authors 	:	Y.J.Xie
//
//
//==============================================================================
//      Module Description :
//      	UART controler
//==============================================================================

`include "xyj_const.v"
`include "timescale.v"

module uart_controler(
		// LPP control
		clk,
		ireset,
		
		// FI
		FI_we,
		FI_data,
		FI_reset,
		FI_done, //added at 11/15/2007 by Y.J.X
		
		//BIST
		bist_en,
		
		// BIRA
		fault_we,
		fault_syn,
		state_we,
		bmp_exceeded,
		bist_reset, //added at 11/15/2007 by Y.J.X
		bist_done,
		repair_finish,
		repairable,
		all_done,
		bist_start,
		
		// uart controler signal
		tx_en,
		
		// uart 
		txd,
		rxd
		
	);
	
	input clk;
	input ireset;
	
	output FI_we;
	output [`XYJ_FID_WIDTH-1:0]FI_data;
	output FI_reset;
	output FI_done;
	
	output bist_en;
	output bist_reset;
	
	input fault_we;
	input [27:0]fault_syn;
	input state_we;
	input bmp_exceeded;
	input bist_done;
	input repair_finish;
	input repairable;
	input all_done;
	input bist_start;
	
	output tx_en;
	
	output txd;
	input rxd;
	
/***********************************************/	
	wire [7:0]uart_data_in_w;
	wire [7:0]uart_data_out_w;
	wire [31:0]data_out_w;
	wire tx_data_w;
	wire uart_re;
	wire uart_we;
	wire rxc;
	wire txc;
	wire all_done;
	
	reg tx_data_r;
	reg [31:0] data_out_r;
	
	reg FI_we_r;
	reg [`XYJ_FID_WIDTH-1:0]FI_data_r;
	reg FI_reset_r;
	reg FI_done_r;
	
	reg bist_reset_r;
	reg bist_en_r;
	
	
	//internal signals
	reg [3:0]data_type;
/***********************************************/
	reg uart_we_r;
	reg uart_re_r;
   
	reg nrxdata;
	reg rxdata1;
	reg rxdata2;
	reg rxdata3;
	reg rxdata4;
	reg rxdata5;
	
	reg ntxdata;
	reg txdata1;
	reg txdata2;
	reg txdata3;
	reg txdata4;
	reg txdata5;

/***********************************************/	
	XYJ_uart XYJ_uart_instance(
             // uart control
             .clk(clk),
             .ireset(ireset),
             .data_in(uart_data_out_w),
             .data_out(uart_data_in_w),
             .uart_re(uart_re),
             .uart_we(uart_we),
             // uart
             .rxd(rxd),
             .txd(txd),
             // state
             .TXC(txc),
             .RXC(rxc)
           );
           
/***********************************************************/
//receive data from uart
/***********************************************************/
					
assign FI_data = FI_data_r;
assign uart_re = uart_re_r ;

// synopsys sync_set_reset "ireset" 
always @(posedge clk)
begin
	if (!ireset)
		data_type <= `NONE_TYPE;
	else begin
		if (rxdata1 && uart_re)
			data_type <= uart_data_in_w[7:4];
		else if (fault_we)
			data_type <= `FAULT_SYN;
		else if (state_we)
			data_type <= {`BIST_STATE,2'b00};
		else if (nrxdata || ntxdata)
			data_type <= data_type;
		else 
			data_type <= `NONE_TYPE;
	end
end

// synopsys sync_set_reset "ireset" 
always @(posedge clk)
begin
	if (!ireset)
		begin
			FI_data_r <= 0;
			nrxdata <= 1'b0;
			rxdata1 <= 1'b0;
			rxdata2 <= 1'b0;
			rxdata3 <= 1'b0;
			rxdata4 <= 1'b0;
			rxdata5 <= 1'b0;
		end
	else 
		begin
			nrxdata <= ~nrxdata & rxc  | nrxdata & ~rxdata5;// & ~bist_en_r
			rxdata1 <= (~rxdata1 & (~nrxdata & rxc) & ~uart_re_r | (uart_re_r | ~rxc) & rxdata1) & ~rxdata5;
			rxdata2 <= (rxdata1 & rxc & ~uart_re_r | (uart_re_r | ~rxc) & rxdata2) & ~rxdata5;
			rxdata3 <= (rxdata2 & rxc & ~uart_re_r | (uart_re_r | ~rxc) & rxdata3) & ~rxdata5;
			rxdata4 <= (rxdata3 & rxc & ~uart_re_r | (uart_re_r | ~rxc) & rxdata4) & ~rxdata5;
			rxdata5 <= ((data_type != `FI_DATA) & rxdata1 | rxdata4) & ~uart_re_r;
			FI_data_r <= ((~nrxdata & rxc  | nrxdata & ~rxdata5) & uart_re_r) ? {FI_data_r[`XYJ_FID_WIDTH-1-8:0],uart_data_in_w} : FI_data_r;		
			uart_re_r <= (~rxdata1 & (~nrxdata & rxc) 
							| rxdata1 & rxc
							| rxdata2 & rxc
							| rxdata3 & rxc)
							& ~uart_re_r & ~rxdata5;
		end
end

// synopsys sync_set_reset "ireset" 
always @(posedge clk)
begin
	if (!ireset)
		begin
			FI_we_r <= 1'b0;
			FI_reset_r <= 1'b1;
			FI_done_r <= 1'b1;
			bist_reset_r <= 1'b1;
			bist_en_r <= 1'b0;
		end
	else 
		begin
			FI_reset_r <= ~(data_type[0] & ~data_type[1] & ~data_type[2] & ~data_type[3] & ~bist_en_r);
			FI_done_r <= data_type[0] & data_type[1] & ~data_type[2] & ~data_type[3] & ~FI_done_r | FI_done_r & FI_reset_r;
			FI_we_r <= (~data_type[0] & data_type[1] & ~data_type[2] & ~data_type[3]) & rxdata5 & ~FI_we_r;
			bist_reset_r <= ~(data_type[0] & ~data_type[1] & data_type[2] & ~data_type[3]);
			bist_en_r <= ~data_type[0] & ~data_type[1] & data_type[2] & ~data_type[3] & ~bist_en_r & FI_done_r | bist_en_r & ~all_done & bist_reset_r;
		end
end

reg bist_reset_neg_reg;
always @(negedge clk) begin
	bist_reset_neg_reg <= bist_reset_r;
end

assign FI_reset = FI_reset_r;
assign FI_we = FI_we_r;
assign FI_done = FI_done_r;
assign bist_reset = bist_reset_neg_reg;
assign bist_en = bist_en_r; 


/***********************************************************/
//transmit data to uart
/***********************************************************/

// synopsys sync_set_reset "ireset" 
always @(posedge clk) begin
	if (!ireset) begin
		tx_data_r <= 1'b0;
		data_out_r <= 32'h00000000;
	end
	else begin
		if (ntxdata) begin
			tx_data_r <= 1'b0;
			data_out_r <= data_out_r;
		end
		else if (fault_we)
			{tx_data_r,data_out_r} <= {1'b1, `FAULT_SYN, fault_syn};
		else if (state_we)
			{tx_data_r,data_out_r} <= {1'b1,`BIST_STATE,bist_start,all_done,bmp_exceeded,bist_done,repairable,repair_finish,24'h000000};
		else 
			{tx_data_r,data_out_r} <= {1'b0, 32'h00000000};
		
	end
end

assign tx_data_w = tx_data_r;
assign data_out_w = data_out_r;

assign uart_data_out_w = txdata1 ? data_out_w[31:24] :
						txdata2 ? data_out_w[23:16] :
						txdata3 ? data_out_w[15:8] :
						txdata4 ? data_out_w[7:0] : 8'h00;
assign uart_we = uart_we_r;

// synopsys sync_set_reset "ireset" 
always @(posedge clk)
begin
	if (!ireset)
		begin
			ntxdata <= 1'b0;
			txdata1 <= 1'b0;
			txdata2 <= 1'b0;
			txdata3 <= 1'b0;
			txdata4 <= 1'b0;
			txdata5 <= 1'b0;
			uart_we_r <= 1'b0;
		end
	else 
		begin
			if (txc)
				begin
					ntxdata <= ~ntxdata & tx_data_w | ntxdata & ~txdata5;
					txdata1 <= (~txdata1 & ~ntxdata & tx_data_w | uart_we_r & txdata1) & ~txdata5;
					txdata2 <= (data_type == `FAULT_SYN) & (txdata1 & ~uart_we_r | uart_we_r & txdata2) & ~txdata5;
					txdata3 <= (data_type == `FAULT_SYN) & (txdata2 & ~uart_we_r | uart_we_r & txdata3) & ~txdata5;
					txdata4 <= (data_type == `FAULT_SYN) & (txdata3 & ~uart_we_r | uart_we_r & txdata4) & ~txdata5;
					txdata5 <= ((data_type != `FAULT_SYN) & txdata1 | txdata4) & ~uart_we_r;
				end
			else
				begin
					ntxdata <= ntxdata;
					txdata1 <= txdata1;
					txdata2 <= txdata2;
					txdata3 <= txdata3;
					txdata4 <= txdata4;
					txdata5 <= txdata5;
				end
			uart_we_r <= ~txdata5 & ((~txdata1 & ~ntxdata & tx_data_w) | (data_type == `FAULT_SYN) & (txdata1 | txdata2 | txdata3)) & txc & ~uart_we_r ;
		end
end

assign tx_en = ~ntxdata & ~nrxdata & txc;				
				

endmodule