router_routing.v

片上网络NOC基于fpga实现的

// ****************************************//
// ****************************************//
// ****** THE ROUTER BASED ON MESH ********// 
// ******    ROUTER VERSION 1.0   *********//
// ******   CODING BY BAYINDALA   *********//
// ******       2008.10.15        *********//
// ****************************************//
// ****************************************//

//file name:router_rouing.v//
`timescale 1ns/1ps
//`include "const_define.v"
//  module of routing logic                              
//  Process the routing problem, including processing the header,payload,tail
      
module module_routing
(		clk, 
		rst, 
		queue_empty,
		req_in, 
		data_in,
		read_queue,///output
		data_out, 
		req_port,
		req_out,
		ack_in
);
parameter DATA=32,CTRL= 4;
//the different states	
parameter 	IDLE=2'b00, 
		READ_ENTITY=2'b01, 
		WAIT_ACK=2'b10;
		
input   	clk,
		rst,
		queue_empty,//input
		req_in,
		ack_in;
input   [DATA+CTRL-1:0]  data_in;

output  read_queue;
output  req_out;		
output  [DATA+CTRL-1:0]  data_out; 
output  [2:0]             req_port;
wire read_queue;
reg    read_queue_reg;
assign read_queue=read_queue_reg;
assign req_out=read_queue;
reg     [DATA+CTRL-1:0]  routing_reg;
reg     [1:0]		  MooreState;
reg     [2:0] 		  rem_port;
wire              is_head, is_tail;

assign data_out   = routing_reg;
assign req_port   = rem_port;
assign is_head    = data_in[DATA];
assign is_tail    = routing_reg[DATA+1];

always @ (posedge clk or posedge rst)
begin
	if (rst)
 	 begin
  	  MooreState <= IDLE;
   	  rem_port   <= 3'b111;    //the status can not  output
         read_queue_reg <= 0;
         routing_reg<=0;
  	 end
	else
  	case (MooreState)
    IDLE: 
        begin
	     routing_reg<=0;
	     //MooreState <= queue_empty ? IDLE:WAIT_ACK;
	     MooreState <= queue_empty ? IDLE:READ_ENTITY;
	     read_queue_reg <= 0;
	 end
    READ_ENTITY:
        begin             
         read_queue_reg <= 1;

         	routing_reg<= is_head ? {data_in[DATA+CTRL-1:DATA+CTRL-4],3'b000,data_in[DATA+CTRL-5:3]}:data_in;
	     	if (is_head) 
            	begin 
			  rem_port <= data_in[2:0];
            	end
       	 if(is_tail)
	     	MooreState <= WAIT_ACK;
	     	else
	     	MooreState <=READ_ENTITY ;
		end 
    WAIT_ACK:
        begin
           read_queue_reg <= 1;
           if (req_in)
             begin               
	           MooreState <= queue_empty ? IDLE:READ_ENTITY;
               //routing_reg<= 0;
               rem_port   <= is_tail? 3'b111:rem_port;  
               //if(is_tail)
               // MooreState <=IDLE; 
		       end
           else
             MooreState <= WAIT_ACK;
	    end  
 	 endcase 
end

endmodule //the end of module_routing