i80386.vhd

Intel微处理器80386的vhdl模拟

    CONSTANT StateT2:       INTEGER := 2;   -- State where NA_n is false (non-pipelined)
    CONSTANT StateT1P:      INTEGER := 3;   -- First state of a pipelined bus cycle
    CONSTANT StateTh:       INTEGER := 4;   -- Hold acknowledge state
    CONSTANT StateT2P:      INTEGER := 5;   -- Subsequent state of a pipelined bus cycle
    CONSTANT StateT2I:      INTEGER := 6;   -- Subsequent state of a potential pipelined
                                            -- bus cycle.
    -- The constants are indexes into the vector State where each constant represents 1 bit of the vector.

-- Internal User Registers
--- General Purpose Data and Address
    SIGNAL EAX: vlbit_1d(31 DOWNTO 0);
    SIGNAL EDX: vlbit_1d(31 DOWNTO 0);
    SIGNAL ECX: vlbit_1d(31 DOWNTO 0);
    SIGNAL EBX: vlbit_1d(31 DOWNTO 0);
    SIGNAL EBP: vlbit_1d(31 DOWNTO 0);
    SIGNAL ESI: vlbit_1d(31 DOWNTO 0);
    SIGNAL EDI: vlbit_1d(31 DOWNTO 0);
    SIGNAL ESP: vlbit_1d(31 DOWNTO 0);
-- NOTE: Create a proceedure that can be called with the appropriate mnemonic
-- to access the appropriate register.  Futher work must be done to implement
-- the 16-bit and 8-bit versions of these registers.

--- Segment Selectors
    SIGNAL CS:  vlbit_1d(15 DOWNTO 0);  -- Code Segment
    SIGNAL SS:  vlbit_1d(15 DOWNTO 0);  -- Stack Segment
    SIGNAL DS:  vlbit_1d(15 DOWNTO 0);  -- Data Segment Module A
    SIGNAL ES:  vlbit_1d(15 DOWNTO 0);  -- Data Segment Structure 1
    SIGNAL FSS: vlbit_1d(15 DOWNTO 0);  -- Data Segment Structure 2
    SIGNAL GS:  vlbit_1d(15 DOWNTO 0);  -- Data Segment Structure 3

--- Segment Descripters
--- These register are associated with each Segment Selector Register and are
--- not visible to the programmer.
--- Instruction Pointer and Flags
    SIGNAL rEIP:        vlbit_1d(31 downto 0) := X"FFFFFFF0";
-- Must create a proceedure to access by mnemonic the IP within the EIP register.
    SIGNAL rEFLAGS:     vlbit_1d(31 downto 0) := B"XXXXXXXXXXXXXXXX0XXXXXXXXX0X0X1X";
    CONSTANT VM:        INTEGER := 0;
    CONSTANT RF:        INTEGER := 0;
    CONSTANT NT:        INTEGER := 0;
    CONSTANT IOPL:      INTEGER := 0;
    CONSTANT xOF:       INTEGER := 0;
    CONSTANT DF:        INTEGER := 0;
    CONSTANT xIF:       INTEGER := 0;
    CONSTANT TF:        INTEGER := 0;
    CONSTANT SF:        INTEGER := 0;
    CONSTANT ZF:        INTEGER := 0;
    CONSTANT AF:        INTEGER := 4;
    CONSTANT PF:        INTEGER := 2;
    CONSTANT CF:        INTEGER := 0;

--- Machine Control
    SIGNAL rCR0:        vlbit_1d(31 downto 0) := X"00000000";
    SIGNAL rCR1:        vlbit_1d(31 downto 0) := X"00000000";
    SIGNAL rCR2:        vlbit_1d(31 downto 0) := X"00000000";
    -- Page Directory Base Register
    SIGNAL rCR3:        vlbit_1d(31 downto 0) := X"00000000";

--- System Address (Memory Mapping Management)
    -- Global Descripter Table Pointer
    SIGNAL rGDTbase:        vlbit_1d(31 downto 0) := X"00000000";
    SIGNAL rGDTlimit:       vlbit_1d(15 downto 0) := X"0000";
    SIGNAL rGDTselector:    vlbit_1d(15 downto 0) := X"0000";
    -- Local Descripter Table Pointer
    SIGNAL rLDTbase:        vlbit_1d(31 downto 0) := X"00000000";
    SIGNAL rLDTlimit:       vlbit_1d(15 downto 0) := X"0000";
    SIGNAL rLDTselector:    vlbit_1d(15 downto 0) := X"0000";
    -- Interrupt Descripter Table Pointer
    SIGNAL rIDTbase:        vlbit_1d(31 downto 0) := X"00000000";
    SIGNAL rIDTlimit:       vlbit_1d(15 downto 0) := X"0000";
    SIGNAL rIDTselector:    vlbit_1d(15 downto 0) := X"0000";
    -- Task State Segment Descripter Table Pointer
    SIGNAL rTSSbase:        vlbit_1d(31 downto 0) := X"00000000";
    SIGNAL rTSSlimit:       vlbit_1d(15 downto 0) := X"0000";
    SIGNAL rTSSselector:    vlbit_1d(15 downto 0) := X"0000";
    -- Page Table Register Files
--  SIGNAL rfPageDir:       vlbit_2d(0 to 1024,31 downto 0);
--  SIGNAL rfPageTable:     vlbit_2d(0 to 1024,31 downto 0);
--- Debug
--- Test

-- 80386 Instruction Set (Supported by this model)

--- Instruction Prefixes
        CONSTANT REP:               INTEGER := 16#F3#;
        CONSTANT REPNE:             INTEGER := 16#F2#;
        CONSTANT LOCK:              INTEGER := 16#F0#;

--- Segment Override Prefixes
        CONSTANT CSsop:             INTEGER := 16#2E#;
        CONSTANT SSsop:             INTEGER := 16#36#;
        CONSTANT DSsop:             INTEGER := 16#3E#;
        CONSTANT ESsop:             INTEGER := 16#26#;
        CONSTANT FSsop:             INTEGER := 16#64#;
        CONSTANT GSsop:             INTEGER := 16#65#;
        CONSTANT OPsop:             INTEGER := 16#66#;
        CONSTANT ADsop:             INTEGER := 16#67#;

--- Data Transfer
        CONSTANT MOV_al_b:          INTEGER := 16#B0#;
        CONSTANT MOV_eax_dw:        INTEGER := 16#B8#; -- mov eax,0000A5A5h
        CONSTANT MOV_ebx_dw:        INTEGER := 16#BB#; -- mov ebx,0FFFFFFF0h
        CONSTANT MOV_ebx_eax:       INTEGER := 16#89#; -- mov [ebx],eax {89,03}
        CONSTANT MOV_eax_ebx:       INTEGER := 16#8B#; -- mov eax,[ebx] {8B,03}
        CONSTANT IN_al:             INTEGER := 16#E4#;
        CONSTANT OUT_al:            INTEGER := 16#E6#;
--- Arithmetic
        CONSTANT ADD_al_b:          INTEGER := 16#04#;
        CONSTANT ADD_ax_w:          INTEGER := 16#05#;
--- Shift/Rotate
        CONSTANT ROL_eax_b:         INTEGER := 16#D1#; -- rol eax,1 {D1,C0}
        CONSTANT ROL_al_1:          INTEGER := 16#D0#;
        CONSTANT ROL_al_n:          INTEGER := 16#C0#;
--- String Manipulation
        CONSTANT INC_eax:           INTEGER := 16#40#;
        CONSTANT INC_ebx:           INTEGER := 16#43#;
--- Bit Manipulation
--- Control Transfer
        CONSTANT JMP_rel_short:     INTEGER := 16#EB#;
        CONSTANT JMP_rel_near:      INTEGER := 16#E9#;
        CONSTANT JMP_intseg_immed:  INTEGER := 16#EA#;
--- High Level Language Support
--- Operating System Support
--- Processor Control
        CONSTANT HLT:               INTEGER := 16#F4#;
        CONSTANT WAITx:             INTEGER := 16#9B#;
        CONSTANT NOP:               INTEGER := 16#90#;

    BEGIN

-- Begin Fault Detection Section
    Faults: PROCESS
    BEGIN
        WAIT UNTIL now > 1;
        assert not bitunknown(CLK2)
            report "Clock {i}: CLK2 (pin F12) is undefined"
            severity FAILURE;
        assert not bitunknown(READY_n)
            report "Control {i}: READY (pin G13) is undefined"
            severity FAILURE;
    END PROCESS Faults;
-- End Fault Detection Section

-- Begin Behavioral Blocks
    -- Port Signals Status Reports Begin
    CLK2status: PROCESS     -- Function:    The first time (after the loading the network)
                            --              the simulation is run, this process will report
                            --              status of the 80386's CLK2 input from the network.

        VARIABLE StartTime:     INTEGER;
        VARIABLE Pwidth:        INTEGER;
        VARIABLE freq:          INTEGER;
    BEGIN
        WAIT UNTIL prising(CLK2);
        StartTime := now;
        WAIT UNTIL prising(CLK2);
        Pwidth := (now - StartTime);
        freq := 10000000 / Pwidth;
        put("CLK2 Pulse Width is=",Pwidth);
        putline(" in 10ths of nS");
        put("CLK2 Frequency is=",freq);
        putline("kHZ");
        WAIT;
    end PROCESS CLK2status;
    -- Port Signals Status Reports End

    -- Internal Control Logic Processes Begin
    GenCLK: PROCESS
    begin
        -- CLK is the 80386's internal clock an is 1/2 of CLK2
        wait until prising(CLK2);
        CLK <= not CLK;
    end PROCESS GenCLK;

    Initialize: PROCESS
    BEGIN
        EAX <= X"00000000";
        rEFLAGS <= X"00000002";
        rEIP <= X"FFFFFFF0";
        rIDTbase <= X"00000000";
        rIDTlimit <= X"03FF";
        State <= vlbit_vector(StateTi);
        IF Debug THEN
            putline("DEBUG: State=RESET");
        END IF;
        WAIT UNTIL pfalling(RESET); -- De-assert the drivers
        IF Debug THEN
            putline("DEBUG: 80386 was successfully Reset.");
        END IF;
        EAX <= X"ZZZZZZZZ";
        rEFLAGS <= X"ZZZZZZZZ";
        rEIP <= X"ZZZZZZZZ";
        rIDTbase <= X"ZZZZZZZZ";
        rIDTlimit <= X"ZZZZ";
        State <= X"ZZZZZZZZ";
        RequestPending <= 'Z';
        WAIT UNTIL prising(RESET);
    end PROCESS Initialize;

    TstateMachine: PROCESS
    VARIABLE nState:    vlbit_1d(31 downto 0) := X"00000000";
    BEGIN
        WAIT UNTIL pfalling(CLK);
        CASE integer(State) is
            WHEN StateTi =>
                IF Debug THEN
                    put("DEBUG: 80386 is in State Ti");
                END IF;
                IF RESET = '0' and RequestPending = Pending THEN
                    nState := vlbit_vector(StateT1);
                    IF Debug THEN
                        putline(", Moving to StateT1");
                    END IF;
                ELSIF RESET = '0' and HOLD = '1' THEN
                    nState := vlbit_vector(StateTh);
                    IF Debug THEN
                        putline(", Moving to StateTh");
                    END IF;
                ELSE
                    nState := vlbit_vector(StateTi);
                    IF Debug THEN
                        IF RESET = '1' THEN
                            putline(", Due to RESET = Asserted");
                        ELSE
                            putline(", Due to NO Requests Pending");
                        END IF;
                    END IF;
                END IF;

            WHEN StateT1 =>
                IF Debug THEN
                    putline("DEBUG: 80386 is in State T1, Moving to StateT2");
                END IF;
                nState := vlbit_vector(StateT2);

            WHEN StateT2 =>
                IF Debug THEN
                    putline("DEBUG: 80386 is in State T2");
                END IF;
                IF READY_n = '0' and HOLD ='0' and RequestPending = Pending THEN
                    nState := vlbit_vector(StateT1);
                ELSIF READY_N = '1' and NA_n = '1' THEN
                    NULL;
                ELSIF (RequestPending = Pending or HOLD = '1') and (READY_N = '1' and NA_n = '0') THEN
                    nState := vlbit_vector(StateT2I);
                ELSIF RequestPending = Pending and HOLD = '0' and READY_N = '1' and NA_n = '0' THEN
                    nState := vlbit_vector(StateT2P);
                ELSIF RequestPending = NotPending and HOLD = '0' and READY_N = '0' THEN
                    nState := vlbit_vector(StateTi);
                ELSIF HOLD = '1' and READY_N = '1' THEN
                    nState := vlbit_vector(StateTh);
                END IF;

            WHEN StateT1P =>
                IF Debug THEN
                    putline("DEBUG: 80386 is in State T1P");
                END IF;
                IF NA_n = '0' and HOLD = '0' and RequestPending = Pending THEN
                    nState := vlbit_vector(StateT2P);
                ELSIF NA_n = '0' and (HOLD = '1' or RequestPending = NotPending) THEN
                    nState := vlbit_vector(StateT2I);
                ELSIF NA_n = '1' THEN
                    nState := vlbit_vector(StateT2);
                END IF;

            WHEN StateTh =>
                IF Debug THEN
                    putline("DEBUG: 80386 is in State Th");
                END IF;
                IF HOLD = '1' THEN
                    NULL;
                ELSIF HOLD = '0' and RequestPending = Pending THEN
                    nState := vlbit_vector(StateT1);
                ELSIF HOLD = '0' and RequestPending = NotPending THEN
                    nState := vlbit_vector(StateTi);
                END IF;

            WHEN StateT2P =>
                IF Debug THEN
                    putline("DEBUG: 80386 is in State T2P");
                END IF;
                IF READY_n = '0' THEN
                    nState := vlbit_vector(StateT1P);
                END IF;

            WHEN StateT2I =>
                IF Debug THEN
                    putline("DEBUG: 80386 is in State T2I");
                END IF;
                IF READY_n = '1' and (RequestPending = NotPending or HOLD = '1') THEN
                    NULL;
                ELSIF READY_n = '1' and RequestPending = Pending and HOLD = '0' THEN
                    nState := vlbit_vector(StateT2P);
                ELSIF READY_n = '0' and HOLD = '1' THEN
                    nState := vlbit_vector(StateTh);
                ELSIF READY_n = '0' and HOLD = '0' and RequestPending = Pending THEN
                    nState := vlbit_vector(StateT1);
                ELSIF READY_n = '0' and HOLD = '0' and RequestPending = NotPending THEN
                    nState := vlbit_vector(StateTi);
                END IF;

            WHEN OTHERS => putline("MODEL ERROR: Invalid State=",State);
        END CASE;
        State <= nState;    -- This is where the next State is actually assigned.
    end PROCESS TstateMachine;