uart_top_struct.vhd

Intel微处理器8088的VHDL实现

-------------------------------------------------------------------------------
--  CPU86 - VHDL CPU8088 IP core                                             --
--  Copyright (C) 2005-2008 HT-LAB                                           --
--                                                                           --
--  Contact/bugs : [e-mail]                                          --
--  Web          : http://www.ht-lab.com                                     --
--                                                                           --
--  CPU86 is released as open-source under the Aladdin Free Public License.  --
--  Contact HT-Lab for commercial applications and/or support contracts.     --
--                                                                           --
--  Full details of the license can be found in the file "cpu86_license.txt" --
--  which is included in the distribution zip file.                          --
-------------------------------------------------------------------------------
-- Simple Wrapper for Opencores 16550 UART                                   --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY uart_top IS
   PORT( 
      BR_clk   : IN     std_logic;
      CTSn     : IN     std_logic  := '1';
      DCDn     : IN     std_logic  := '1';
      DSRn     : IN     std_logic  := '1';
      RIn      : IN     std_logic  := '1';
      WR       : IN     std_logic;
      abus     : IN     std_logic_vector (2 DOWNTO 0);
      clk      : IN     std_logic;
      csn      : IN     std_logic;
      dbus_in  : IN     std_logic_vector (7 DOWNTO 0);
      resetn   : IN     std_logic;
      sRX      : IN     std_logic;
      B_CLK    : OUT    std_logic;
      DTRn     : OUT    std_logic;
      IRQ      : OUT    std_logic;
      OUT1n    : OUT    std_logic;
      OUT2n    : OUT    std_logic;
      RTSn     : OUT    std_logic;
      RXRDYn   : OUT    std_logic;
      TXRDYn   : OUT    std_logic;
      dbus_out : OUT    std_logic_vector (7 DOWNTO 0);
      stx      : OUT    std_logic
   );

-- Declarations

END uart_top ;

ARCHITECTURE struct OF uart_top IS

   -- Architecture declarations
   signal csd_s : std_logic;

   -- Internal signal declarations
   SIGNAL ADD : std_logic_vector(2 DOWNTO 0);
   SIGNAL CS  : std_logic;
   SIGNAL D   : std_logic_vector(7 DOWNTO 0);
   SIGNAL RD  : std_logic_vector(7 DOWNTO 0);
   SIGNAL rst : std_logic;


   -- Component Declarations
   COMPONENT gh_uart_16550
   PORT (
      ADD    : IN     std_logic_vector (2 DOWNTO 0);
      BR_clk : IN     std_logic;
      CS     : IN     std_logic;
      CTSn   : IN     std_logic  := '1';
      D      : IN     std_logic_vector (7 DOWNTO 0);
      DCDn   : IN     std_logic  := '1';
      DSRn   : IN     std_logic  := '1';
      RIn    : IN     std_logic  := '1';
      WR     : IN     std_logic;
      clk    : IN     std_logic;
      rst    : IN     std_logic;
      sRX    : IN     std_logic;
      B_CLK  : OUT    std_logic;
      DTRn   : OUT    std_logic;
      IRQ    : OUT    std_logic;
      OUT1n  : OUT    std_logic;
      OUT2n  : OUT    std_logic;
      RD     : OUT    std_logic_vector (7 DOWNTO 0);
      RTSn   : OUT    std_logic;
      RXRDYn : OUT    std_logic;
      TXRDYn : OUT    std_logic;
      stx    : OUT    std_logic
   );
   END COMPONENT;

BEGIN
   -- Architecture concurrent statements
   -- HDL Embedded Text Block 1 eb1
   -- eb1 1         
   -- Simple gh_uart_16550 wrapper
   rst <= not resetn;      -- externally use active low reset
   
   -- some name changes, not realy required
   D <= dbus_in;      
   ADD <= abus;
   
   process(clk,resetn)
      begin
       if resetn='0' then
          csd_s  <= '1';
          CS <= '0';
       elsif rising_edge(clk) then 
          csd_s  <= csn;
          if csn='0' AND csd_s='1'   then
             CS  <='1';
          else
             CS <='0';
          end if;
       end if;
   end process;  
   
   ---------------------------------------------------------------------------
   -- Latch read data before feeding to the output databus. This is required 
   -- because the output data is required to be valid until the rising edge
   -- of rdn.
   ---------------------------------------------------------------------------
   process(clk,resetn)
      begin
       if resetn='0' then
           dbus_out  <= (others => '0');
       elsif rising_edge(clk) then 
          if (csn='0' AND csd_s='1') then  -- CS='1'
             dbus_out <= RD; 
         end if;
       end if;
   end process;                                                                     


   -- Instance port mappings.
   U_0 : gh_uart_16550
      PORT MAP (
         clk    => clk,
         BR_clk => BR_clk,
         rst    => rst,
         CS     => CS,
         WR     => WR,
         ADD    => ADD,
         D      => D,
         sRX    => sRX,
         CTSn   => CTSn,
         DSRn   => DSRn,
         RIn    => RIn,
         DCDn   => DCDn,
         stx    => stx,
         DTRn   => DTRn,
         RTSn   => RTSn,
         OUT1n  => OUT1n,
         OUT2n  => OUT2n,
         TXRDYn => TXRDYn,
         RXRDYn => RXRDYn,
         IRQ    => IRQ,
         B_CLK  => B_CLK,
         RD     => RD
      );

END struct;