biu_struct.vhd

Intel微处理器8088的VHDL实现

         nmipre_s <= "00";      
      elsif rising_edge(clk) then
         nmipre_s <= nmipre_s(0) & nmi;
      end if;
   end process;
   
   -- set/reset FF
   process(reset, clk) -- ireg
   begin
      if (reset='1') then
         nmi_s <= '0';   
      elsif rising_edge(clk) then
       if (irq_clr='1') then
          nmi_s <= '0';   
       else 
           nmi_s <= nmi_s or ((not nmipre_s(1)) and nmipre_s(0));
       end if;
      end if;
   end process;
   
   -- Instruction trace flag, the trace flag is latched by the decode_state signal. This will
   -- result in the instruction after setting the trace flag not being traced (required).
   -- The instr_trace_s flag is not set if the current instruction is a HLT
   process(reset, clk) 
   begin
      if (reset='1') then
         instr_trace_s <= '0';   
      elsif rising_edge(clk) then
         if (decode_state='1' and halt_instr='0') then
             instr_trace_s <= status.flag(8);   
          end if;
      end if;
   end process;
   
   -- int0_req=Divider/0 error . ver 0.75
   -- status(8)=TF
   -- status(9)=IF
   irq_req_s <= '1' when ((status.div_err='1' or instr_trace_s='1' or nmi_s='1' or (status.flag(9)='1' and intr='1')) and irq_block='0') else '0';                                      

   -- set/reset FF
   process(reset, clk) -- ireg
       begin
          if (reset='1') then
               irq_req_internal <= '0';   
           elsif rising_edge(clk) then
               if (irq_clr='1') then
                   irq_req_internal <= '0';   
               elsif irq_req_s='1' then
                  irq_req_internal <= '1';
               end if;
          end if;
   end process;
   
   process (reset,clk)
       begin
          if reset='1' then
             irq_type <= (others => '0');       -- Don't care value
          elsif rising_edge(clk) then
            if irq_req_internal='1' then
                 if nmi_s='1' then
                     irq_type <= "10";         -- NMI result in INT2
                 elsif status.flag(8)='1' then
                     irq_type <= "01";         -- TF result in INT1
                 else
                     irq_type <= "00";         -- INTR result in INT <DBUS>
                 end if;
            end if;
         end if;
   end process;

   -- HDL Embedded Text Block 9 rwselect
   -- wrselect 9  
   
   ---------------------------------------------------------------------------
   -- Delayed signals
   ---------------------------------------------------------------------------
   process(clk,reset)
      begin
       if reset='1' then
           latchrw_d_s  <= '0';
           latchclr_d_s <= '0';
       elsif rising_edge(clk) then 
           latchrw_d_s  <= latchrw; 
           latchclr_d_s <= latchclr;        
       end if;
   end process;
   
   
   ---------------------------------------------------------------------------
   -- IO/~M strobe latch
   ---------------------------------------------------------------------------
   process(clk,reset)
      begin
         if reset='1' then
            iom_s <= '0';
         elsif rising_edge(clk) then 
            if latchrw='1' and muxabus/="00" then   
                 iom_s <= iomem;
            elsif latchrw='1' then
                 iom_s <= '0';        
            end if;
         end if;
   end process;
   iom <= iom_s;
   
   
   ---------------------------------------------------------------------------
   -- Shifted WR strobe latch, to add some address and data hold time the WR
   -- strobe is negated .5 clock cycles before address and data changes. This
   -- is implemented using the falling edge of the clock. Generally using
   -- both edges of a clock is not recommended.  If this is not desirable
   -- use the latchclr signal with the rising edge of clk. This will result
   -- in a full clk cycle for the data hold.
   ---------------------------------------------------------------------------
   process(clk,reset)                      -- note wr should be 1 clk cycle after latchrw
      begin
         if reset='1' then
            wran  <= '1';
   
         elsif falling_edge(clk) then      -- wran is negated 0.5 cycle before data&address changes
            if latchclr_d_s='1' then    
               wran <= '1';      
            elsif wr_s='1' then   
               wran<='0';
            end if;
   
   --      elsif rising_edge(clk) then     -- wran negated 1 clk cycle before data&address changes
   --         if latchclr='1' then             
   --            wran <= '1';      
   --         elsif wr_s='1' then   
   --            wran<='0';
   --         end if;
   
         end if;
   end process;
   
   ---------------------------------------------------------------------------
   -- WR strobe latch. This signal can be use to drive the tri-state drivers 
   -- and will result in a data hold time until the end of the write cycle.
   ---------------------------------------------------------------------------
   process(clk,reset)                      
      begin
         if reset='1' then
          wrn <= '1';                     
         elsif rising_edge(clk) then 
            if latchclr_d_s='1' then        -- Change wrn at the same time as addr changes
               wrn <= '1';      
            elsif wr_s='1' then   
               wrn<='0';
            end if;
         end if;
   end process;
   
   
   ---------------------------------------------------------------------------
   -- RD strobe latch   
   -- rd is active low and connected to top entity      
   -- Use 1 clk delayed latchrw_d_s signal
   -- Original signals were rd_data_s and rd_code_s, new signals rddata_s and 
   -- rdcode_s.
   -- Add flushreq_s, prevend rd signal from starting 
   ---------------------------------------------------------------------------
   process(reset,clk)
   begin
      if reset='1' then
         rdn <= '1';
         latchmd_s <= '0';
      elsif rising_edge(clk) then
          if latchclr_d_s='1' then
              rdn <= '1';
              latchmd_s <= '0';
          elsif latchrw_d_s='1' then
                latchmd_s <= rddata_s;
                -- Bug reported by Rick Kilgore
             -- ver 0.69, stops RD from being asserted during second inta
                rdn <= not((rdcode_s or rddata_s) AND NOT intack); 
                 
        -- The next second was added to create a updown pulse on the rd strobe
        -- during a flush action. This will result in a dummy read cycle (unavoidable?)
         elsif latchrw='1' then
             latchmd_s <= rddata_s;
             rdn <= not(rdcode_s or rddata_s);  
         end if;
      end if;
   end process;
   
   
   ---------------------------------------------------------------------------
   -- Second INTA strobe latch   
   ---------------------------------------------------------------------------
   process(reset,clk)
   begin
      if reset='1' then
        inta2_s<= '0';
      elsif rising_edge(clk) then         
          if latchclr_d_s='1' then
              inta2_s <= '0';
          elsif latchrw_d_s='1' then
              inta2_s <= intack;
         end if;
      end if;
   end process;
   
   inta <= not (inta2_s OR inta1_internal); 
   
   ---------------------------------------------------------------------------
   -- Databus stearing for the datapath input
   -- mdbus_out(31..16) is only used for "int x", the value si used to load 
   -- ipreg at the same time as loading cs.
   -- Note mdbus must be valid (i.e. contain dbus value) before rising edge
   -- of wrn/rdn
   ---------------------------------------------------------------------------
   process(clk,reset) 
      begin
         if reset='1' then
            mdbus_out <= (others => '0');
         elsif rising_edge(clk) then 
            if latchmd_s='1' then   
                if word='0' then                   -- byte read
                     mdbus_out <= X"00" & dbus_in;
                else
                   if muxabus="00" then            -- first cycle of word read
                      mdbus_out(15 downto 8) <= dbus_in;
                   else                            -- Second cycle 
                      mdbus_out(7 downto 0) <= dbus_in;
                   end if;               
                end if;        
            end if;
         end if;
   end process;


   -- Instance port mappings.
   fsm : biufsm
      PORT MAP (
         clk          => clk,
         flush_coming => flush_coming,
         flush_req    => flush_req,
         irq_req      => irq_req_internal,
         irq_type     => irq_type,
         opc_req      => opc_req,
         read_req     => read_req,
         reg1freed    => reg1freed,
         reg4free     => reg4free,
         regnbok      => regnbok,
         reset        => reset,
         w_biufsm_s   => w_biufsm_s,
         write_req    => write_req,
         addrplus4    => addrplus4,
         biu_error    => biu_error,
         biu_status   => biu_status,
         irq_ack      => irq_ack,
         irq_clr      => irq_clr,
         latchabus    => latchabus,
         latchclr     => latchclr,
         latchm       => latchm,
         latcho       => latcho_internal,
         latchrw      => latchrw,
         ldposplus1   => ldposplus1,
         muxabus      => muxabus,
         rdcode_s     => rdcode_s,
         rddata_s     => rddata_s,
         regplus1     => regplus1,
         rw_ack       => rw_ack,
         wr_s         => wr_s,
         flush_ack    => flush_ack_internal,
         inta1        => inta1_internal
      );
   I4 : formatter
      PORT MAP (
         lutbus   => lutbus,
         mux_addr => mux_addr,
         mux_data => mux_data,
         mux_reg  => mux_reg,
         nbreq    => nbreq
      );
   shift : regshiftmux
      PORT MAP (
         clk        => clk,
         dbus_in    => dbus_in,
         flush_req  => flush_req,
         latchm     => latchm,
         latcho     => latcho_internal,
         mux_addr   => mux_addr,
         mux_data   => mux_data,
         mux_reg    => mux_reg,
         nbreq      => nbreq,
         regplus1   => regplus1,
         ldposplus1 => ldposplus1,
         reset      => reset,
         irq        => irq_ack,
         inta1      => inta1_internal,
         inta2_s    => inta2_s,
         irq_type   => irq_type,
         instr      => instr,
         halt_instr => halt_instr,
         lutbus     => lutbus,
         reg1free   => reg4free,
         reg1freed  => reg1freed,
         regnbok    => regnbok
      );

   -- Implicit buffered output assignments
   latcho    <= latcho_internal;
   flush_ack <= flush_ack_internal;
   irq_req   <= irq_req_internal;
   inta1     <= inta1_internal;

END struct;