biu_struct.vhd

Intel微处理器8088的VHDL实现

-- -----------------------------------------------------------------------------
--   CPU86 - VHDL CPU8088 IP core                                             --
--   Copyright (C) 2005-2008 HT-LAB                                           --
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--   Contact/bugs : http://www.ht-lab.com/misc/feedback.html                  --
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--                                                                            --
--   CPU86 is released as open-source under the Aladdin Free Public License.  --
--   Contact HT-Lab for commercial applications and/or support contracts.     --
--                                                                            --
--   Full details of the license can be found in the file "cpu86_license.txt" --
--   which is included in the distribution zip file.                          --
-- -----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.ALL;

USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;

ENTITY biu IS
   PORT( 
      abusdp_in    : IN     std_logic_vector (19 DOWNTO 0);
      clk          : IN     std_logic;
      dbus_in      : IN     std_logic_vector (7 DOWNTO 0);
      dbusdp_in    : IN     std_logic_vector (15 DOWNTO 0);
      decode_state : IN     std_logic;
      flush_coming : IN     std_logic;
      flush_req    : IN     std_logic;
      intack       : IN     std_logic;
      intr         : IN     std_logic;
      iomem        : IN     std_logic;
      irq_block    : IN     std_logic;
      nmi          : IN     std_logic;
      opc_req      : IN     std_logic;
      read_req     : IN     std_logic;
      reset        : IN     std_logic;
      status       : IN     status_out_type;
      word         : IN     std_logic;
      write_req    : IN     std_logic;
      abus         : OUT    std_logic_vector (19 DOWNTO 0);
      biu_error    : OUT    std_logic;
      dbus_out     : OUT    std_logic_vector (7 DOWNTO 0);
      flush_ack    : OUT    std_logic;
      instr        : OUT    instruction_type;
      inta         : OUT    std_logic;
      inta1        : OUT    std_logic;
      iom          : OUT    std_logic;
      irq_req      : OUT    std_logic;
      latcho       : OUT    std_logic;
      mdbus_out    : OUT    std_logic_vector (15 DOWNTO 0);
      rdn          : OUT    std_logic;
      rw_ack       : OUT    std_logic;
      wran         : OUT    std_logic;
      wrn          : OUT    std_logic
   );

-- Declarations

END biu ;

ARCHITECTURE struct OF biu IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL abus_s        : std_logic_vector(19 DOWNTO 0);
   SIGNAL abusbiu       : std_logic_vector(19 DOWNTO 0);
   SIGNAL abusdp_inp1_s : std_logic_vector(19 DOWNTO 0);
   SIGNAL abusmux_s     : std_logic_vector(19 DOWNTO 0);
   SIGNAL abusplus4_s   : std_logic_vector(19 DOWNTO 0);
   SIGNAL addrplus4     : std_logic;
   SIGNAL biu_status    : std_logic_vector(2 DOWNTO 0);
   SIGNAL halt_instr    : std_logic;
   SIGNAL inta2_s       : std_logic;                        -- Second INTA pulse, used to latch 8 bist vector
   SIGNAL irq_ack       : std_logic;
   SIGNAL irq_clr       : std_logic;
   SIGNAL irq_type      : std_logic_vector(1 DOWNTO 0);
   SIGNAL latchabus     : std_logic;
   SIGNAL latchclr      : std_logic;
   SIGNAL latchm        : std_logic;
   SIGNAL latchrw       : std_logic;
   SIGNAL ldposplus1    : std_logic;
   SIGNAL lutbus        : std_logic_vector(15 DOWNTO 0);
   SIGNAL mux_addr      : std_logic_vector(2 DOWNTO 0);
   SIGNAL mux_data      : std_logic_vector(3 DOWNTO 0);
   SIGNAL mux_reg       : std_logic_vector(2 DOWNTO 0);
   SIGNAL muxabus       : std_logic_vector(1 DOWNTO 0);
   SIGNAL nbreq         : std_logic_vector(2 DOWNTO 0);
   SIGNAL rdcode_s      : std_logic;
   SIGNAL rddata_s      : std_logic;
   SIGNAL reg1freed     : std_logic;                        -- Delayed version (1 clk) of reg1free
   SIGNAL reg4free      : std_logic;
   SIGNAL regnbok       : std_logic;
   SIGNAL regplus1      : std_logic;
   SIGNAL w_biufsm_s    : std_logic;
   SIGNAL wr_s          : std_logic;

   -- Implicit buffer signal declarations
   SIGNAL latcho_internal    : std_logic;
   SIGNAL flush_ack_internal : std_logic;
   SIGNAL irq_req_internal   : std_logic;
   SIGNAL inta1_internal     : std_logic;


   signal nmi_s : std_logic;
   signal nmipre_s : std_logic_vector(1 downto 0); -- metastability first FF for nmi
   signal outbus_s : std_logic_vector(7 downto 0); -- used in out instr. bus streering
   signal latchmd_s : std_logic; -- internal rdl_s signal
   signal abusdp_inp1l_s: std_logic_vector(19 downto 0);
   signal latchrw_d_s: std_logic; -- latchrw delayed 1 clk cycle
   signal latchclr_d_s: std_logic; -- latchclr delayed 1 clk cycle
   signal iom_s : std_logic;
   signal instr_trace_s : std_logic; -- TF latched by exec_state pulse
   signal irq_req_s : std_logic;

   -- Component Declarations
   COMPONENT biufsm
   PORT (
      clk          : IN     std_logic ;
      flush_coming : IN     std_logic ;
      flush_req    : IN     std_logic ;
      irq_req      : IN     std_logic ;
      irq_type     : IN     std_logic_vector (1 DOWNTO 0);
      opc_req      : IN     std_logic ;
      read_req     : IN     std_logic ;
      reg1freed    : IN     std_logic ;
      reg4free     : IN     std_logic ;
      regnbok      : IN     std_logic ;
      reset        : IN     std_logic ;
      w_biufsm_s   : IN     std_logic ;
      write_req    : IN     std_logic ;
      addrplus4    : OUT    std_logic ;
      biu_error    : OUT    std_logic ;
      biu_status   : OUT    std_logic_vector (2 DOWNTO 0);
      irq_ack      : OUT    std_logic ;
      irq_clr      : OUT    std_logic ;
      latchabus    : OUT    std_logic ;
      latchclr     : OUT    std_logic ;
      latchm       : OUT    std_logic ;
      latcho       : OUT    std_logic ;
      latchrw      : OUT    std_logic ;
      ldposplus1   : OUT    std_logic ;
      muxabus      : OUT    std_logic_vector (1 DOWNTO 0);
      rdcode_s     : OUT    std_logic ;
      rddata_s     : OUT    std_logic ;
      regplus1     : OUT    std_logic ;
      rw_ack       : OUT    std_logic ;
      wr_s         : OUT    std_logic ;
      flush_ack    : BUFFER std_logic ;
      inta1        : BUFFER std_logic 
   );
   END COMPONENT;
   COMPONENT formatter
   PORT (
      lutbus   : IN     std_logic_vector (15 DOWNTO 0);
      mux_addr : OUT    std_logic_vector (2 DOWNTO 0);
      mux_data : OUT    std_logic_vector (3 DOWNTO 0);
      mux_reg  : OUT    std_logic_vector (2 DOWNTO 0);
      nbreq    : OUT    std_logic_vector (2 DOWNTO 0)
   );
   END COMPONENT;
   COMPONENT regshiftmux
   PORT (
      clk        : IN     std_logic ;
      dbus_in    : IN     std_logic_vector (7 DOWNTO 0);
      flush_req  : IN     std_logic ;
      latchm     : IN     std_logic ;
      latcho     : IN     std_logic ;
      mux_addr   : IN     std_logic_vector (2 DOWNTO 0);
      mux_data   : IN     std_logic_vector (3 DOWNTO 0);
      mux_reg    : IN     std_logic_vector (2 DOWNTO 0);
      nbreq      : IN     std_logic_vector (2 DOWNTO 0);
      regplus1   : IN     std_logic ;
      ldposplus1 : IN     std_logic ;
      reset      : IN     std_logic ;
      irq        : IN     std_logic ;
      inta1      : IN     std_logic ;                   -- Added for ver 0.71
      inta2_s    : IN     std_logic ;
      irq_type   : IN     std_logic_vector (1 DOWNTO 0);
      instr      : OUT    instruction_type ;
      halt_instr : OUT    std_logic ;
      lutbus     : OUT    std_logic_vector (15 DOWNTO 0);
      reg1free   : BUFFER std_logic ;
      reg1freed  : BUFFER std_logic ;                   -- Delayed version (1 clk) of reg1free
      regnbok    : OUT    std_logic 
   );
   END COMPONENT;


BEGIN
   -- Architecture concurrent statements
   -- HDL Embedded Text Block 1 abusreg
   -------------------------------------------------------------------------
   -- eb1 1 BIU Address Register    
   -------------------------------------------------------------------------
   process(reset,clk)
   begin
      if reset='1' then
         abusbiu <= RESET_VECTOR_C(19 downto 0);
      elsif rising_edge(clk) then
         if latchabus='1' then
            abusbiu <= abusmux_s;
          end if;
      end if;
   end process;

   -- HDL Embedded Text Block 2 eb1
   -- eb1 2  
   -------------------------------------------------------------------------
   -- Latch datapath address+4 for mis-aligned R/W    
   -------------------------------------------------------------------------
   process(reset,clk)
   begin
      if reset='1' then
         abusdp_inp1l_s <= RESET_VECTOR_C;
      elsif rising_edge(clk) then
            if latchrw='1' then    -- Latch Address 
               abusdp_inp1l_s<= abusdp_inp1_s;                        
            end if;
      end if;
   end process;
   
   process(abusdp_in, abusdp_inp1l_s,abusbiu,muxabus)
   begin
      case muxabus is
         when "01"   => abus_s <= abusdp_in;      
         when "10"   => abus_s <= abusdp_inp1l_s;      -- Add 1 if odd address and write word
         when others => abus_s <= abusbiu;       -- default to BIU word address
      end case;
   end process;
   
   -------------------------------------------------------------------------
   -- Address/Databus Latch    
   -------------------------------------------------------------------------
   process(reset,clk)
   begin
      if reset='1' then
         abus <= RESET_VECTOR_C;
      elsif rising_edge(clk) then
            if latchrw='1' then                     -- Latch Address 
               abus <= abus_s;                        
            end if;
      end if;
   end process;

   -- HDL Embedded Text Block 3 plus1b
   -- plus1 3  
   abusplus4_s <= abusbiu + '1'; -- Ax..A2 "100";

   -- HDL Embedded Text Block 4 eb2
   -- eb1 2      
   abusmux_s <= abusplus4_s when addrplus4='1' else abusdp_in(19 downto 0);

   -- HDL Embedded Text Block 5 dbuslatch
   -------------------------------------------------------------------------
   -- Databus Latch    
   -------------------------------------------------------------------------
   process(reset,clk)
   begin
      if reset='1' then
         dbus_out   <= DONTCARE(7 downto 0);          
      elsif rising_edge(clk) then
            if latchrw='1' then                  -- Latch Data from DataPath
               dbus_out <= outbus_s; 
            end if;
      end if;
   end process;
   
   
   ---------------------------------------------------------------------------
   -- OUT instruction bus steering
   -- IO/~M & A[1:0] 
   ---------------------------------------------------------------------------
   process(dbusdp_in,abus_s)
      begin
          if abus_s(0)='0' then
            outbus_s <= dbusdp_in(7 downto 0);     -- D0 
         else
            outbus_s <= dbusdp_in(15 downto 8);     -- D1
         end if;
   end process;

   -- HDL Embedded Text Block 6 plus1a
   -- plus1 3  
   abusdp_inp1_s <= abusdp_in + '1';--"100"; -- + 1 word;

   -- HDL Embedded Text Block 7 eb3
   -- eb3 7   
   ---------------------------------------------------------------------------
   -- Latch word for BIU FSM
   ---------------------------------------------------------------------------
   process(clk,reset)
      begin
         if reset='1' then
           w_biufsm_s<='0';
         elsif rising_edge(clk) then 
            if latchrw='1' then   
              w_biufsm_s<=word;
            end if;
         end if;
   end process;

   -- HDL Embedded Text Block 8 eb4
   -- eb4 8 
   -- metastability sync
   process(reset,clk) -- ireg
   begin
      if reset='1' then