📄 cpu86_top_struct.vhd
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-------------------------------------------------------------------------------
-- --
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2005-2008 HT-LAB --
-- --
-- Contact/bugs : cpu86@ht-lab.com --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the Aladdin Free Public License. --
-- Contact HT-Lab for commercial applications and/or support contracts. --
-- --
-- Full details of the license can be found in the file "cpu86_license.txt" --
-- which is included in the distribution zip file. --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Instantiate CPU86 + Opencores 16550 UART --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY cpu86_top IS
PORT(
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
RESET : IN std_logic;
RXD : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
RTS : OUT std_logic;
TXD : OUT std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
cpuerror : OUT std_logic;
csramn : OUT std_logic;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
rdn : OUT std_logic;
resoutn : OUT std_logic;
wrn : OUT std_logic
);
-- Declarations
END cpu86_top ;
ARCHITECTURE struct OF cpu86_top IS
-- Architecture declarations
signal csromn : std_logic;
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL sel_s : std_logic_vector(1 DOWNTO 0);
SIGNAL step_sw : std_logic;
SIGNAL test : std_logic;
SIGNAL wrcom : std_logic;
-- Implicit buffer signal declarations
SIGNAL resoutn_internal : std_logic;
SIGNAL dbus_out_internal : std_logic_vector (7 DOWNTO 0);
SIGNAL abus_internal : std_logic_vector (19 DOWNTO 0);
SIGNAL wrn_internal : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
WR : IN std_logic ;
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
resetn : IN std_logic ;
sRX : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
RXRDYn : OUT std_logic ;
TXRDYn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
sTX : OUT std_logic
);
END COMPONENT;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 5 mux1
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom)
begin
case sel_s is
when "01" => dbus_in_cpu <= dbus_com1; -- UART
when "10" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when others => dbus_in_cpu <= dbus_in; -- Embedded SRAM
end case;
end process;
-- HDL Embedded Text Block 8 clogic1
clk <= CLOCK_40MHZ;
por <= RESET;
wrcom <= not wrn_internal;
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
-- COM2, 0x2F8-0x2FF
cscom1 <= '0' when (abus_internal(15 downto 3)="0000001111111" AND iom='1') else '1';
--cscom2 <= '0' when (abus_internal(15 downto 3)="0000001011111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus_internal(19 downto 8)=X"FFF") AND iom='0') else '1';
-- SRAM 1MByte-256 bytes for the bootstrap
csramn <='0' when (csromn='1' AND iom='0') else '1';
-- ModuleWare code(v1.9) for instance 'U_4' of 'gnd'
nmi <= '0';
-- ModuleWare code(v1.9) for instance 'U_5' of 'gnd'
intr <= '0';
-- ModuleWare code(v1.9) for instance 'U_6' of 'gnd'
test <= '0';
-- ModuleWare code(v1.9) for instance 'U_7' of 'gnd'
step_sw <= '0';
-- ModuleWare code(v1.9) for instance 'U_8' of 'gnd'
DCDn <= '0';
-- ModuleWare code(v1.9) for instance 'U_9' of 'gnd'
DSRn <= '0';
-- ModuleWare code(v1.9) for instance 'U_10' of 'gnd'
RIn <= '0';
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus_internal,
cpuerror => cpuerror,
dbus_out => dbus_out_internal,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn_internal,
wran => OPEN,
wrn => wrn_internal
);
U_0 : uart_top
PORT MAP (
BR_clk => clk,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
WR => wrcom,
abus => abus_internal(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out_internal,
resetn => resoutn_internal,
sRX => RXD,
B_CLK => OPEN,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => OPEN,
OUT2n => OPEN,
RTSn => RTS,
RXRDYn => OPEN,
TXRDYn => OPEN,
dbus_out => dbus_com1,
sTX => TXD
);
U_11 : bootstrap
PORT MAP (
abus => abus_internal(7 DOWNTO 0),
dbus => dbus_rom
);
-- Implicit buffered output assignments
resoutn <= resoutn_internal;
dbus_out <= dbus_out_internal;
abus <= abus_internal;
wrn <= wrn_internal;
END struct;
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