ipregister_rtl.vhd

Intel微处理器8088的VHDL实现

-------------------------------------------------------------------------------
--  CPU86 - VHDL CPU8088 IP core                                             --
--  Copyright (C) 2005-2008 HT-LAB                                           --
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--  CPU86 is released as open-source under the Aladdin Free Public License.  --
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--                                                                           --
--  Full details of the license can be found in the file "cpu86_license.txt" --
--  which is included in the distribution zip file.                          --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

USE work.cpu86pack.ALL;

ENTITY ipregister IS
   PORT( 
      clk   : IN     std_logic;
      ipbus : IN     std_logic_vector (15 DOWNTO 0);
      reset : IN     std_logic;
      wrip  : IN     std_logic;
      ipreg : OUT    std_logic_vector (15 DOWNTO 0)
   );

-- Declarations

END ipregister ;


architecture rtl of ipregister is

signal ipreg_s : std_logic_vector(15 downto 0);

begin

----------------------------------------------------------------------------
-- Instruction Pointer Register
----------------------------------------------------------------------------
process (clk, reset)
    begin 
        if reset='1' then
            ipreg_s <= RESET_IP_C; -- See cpupack
        elsif rising_edge(clk) then
            if (wrip='1') then                                      
                ipreg_s<= ipbus;  
            end if; 
        end if; 
end process;  

ipreg <= ipreg_s;

end rtl;