biufsm_fsm.vhd

Intel微处理器8088的VHDL实现

      irq_clr <= '0';
      latchabus <= '0';
      latchclr <= '0';
      latchm <= '0';
      latcho <= '0';
      latchrw <= '0';
      ldposplus1 <= '0';
      muxabus <= "00";
      rdcode_s <= '0';
      rddata_s <= '0';
      regplus1 <= '0';
      rw_ack <= '0';
      wr_s <= '0';
      flush_ack <= '0';
      inta1 <= '0';

      -- Combined Actions
      CASE current_state IS
         WHEN Sreset => 
            latchrw <= '1' ;
            next_state <= Srdopc;
         WHEN Sws => 
            IF (flush_req = '1') THEN 
               next_state <= Sflush1;
            ELSIF (ws_s=MAX_WS-1) THEN 
               next_state <= Smaxws;
            ELSE
               next_state <= Sws;
            END IF;
         WHEN Smaxws => 
            latchabus<='1';
            addrplus4<='1'; 
            latchclr <= '1' ;
            ldposplus1<='1';
            IF (flush_req = '1') THEN 
               next_state <= Sflush1;
            ELSE
               next_state <= Sack;
            END IF;
         WHEN Sack => 
            latchm<=reg1freed; 
            regplus1<='1';
            IF (write_req = '1') THEN 
               muxabus <="01";
               latchrw <= '1' ;
               next_state <= Swrite;
            ELSIF (read_req = '1') THEN 
               muxabus <="01";
               latchrw <= '1' ;
               next_state <= Sread;
            ELSIF (flush_req = '1') THEN 
               next_state <= Sflush1;
            ELSIF (irq_req='1' AND opc_req='1') THEN 
               irq_ack<='1';
               next_state <= Sint;
            ELSIF (reg4free = '1' AND
                   flush_coming='0' AND
                   irq_req='0') THEN 
               latchrw <= '1' ;
               next_state <= Srdopc;
            ELSIF (regnbok = '0' and 
                   reg4free = '0') THEN 
               next_state <= Serror;
            ELSE
               next_state <= Sfull;
            END IF;
         WHEN Srdopc => 
            rdcode_s <= '1';
            latcho <= regnbok and opc_req;
            IF (flush_req = '1') THEN 
               next_state <= Sflush1;
            ELSIF (ws_s/=MAX_WS) THEN 
               next_state <= Sws;
            ELSE
               next_state <= Smaxws;
            END IF;
         WHEN Serror => 
            biu_error_int <= '1';
            next_state <= Serror;
         WHEN Swrite => 
            wr_s <= '1';
            IF (ws_s/=MAX_WS) THEN 
               next_state <= Swsw;
            ELSE
               next_state <= Smaxwsw;
            END IF;
         WHEN Swsw => 
            latcho <= regnbok and opc_req;
            IF (ws_s=MAX_WS-1) THEN 
               next_state <= Smaxwsw;
            ELSE
               next_state <= Swsw;
            END IF;
         WHEN Smaxwsw => 
            latcho <= regnbok and opc_req;
            latchclr <= '1' ;
            rw_ack<= not rwmem3_s;
            next_state <= Sackw;
         WHEN Sackw => 
            latcho <= regnbok and opc_req;
            IF (rwmem3_s = '1') THEN 
               muxabus <="10";
               latchrw<='1';
               next_state <= Swrodd;
            ELSIF (flush_req = '1') THEN 
               next_state <= Sflush1;
            ELSIF (irq_req='1' AND opc_req='1') THEN 
               irq_ack<='1';
               next_state <= Sint;
            ELSIF (reg4free = '1' ) THEN 
               muxabus <="00";
               latchrw<='1';
               next_state <= Srdopc;
            ELSIF (flush_coming='1' OR
                   (irq_req='1' AND opc_req='0')) THEN 
               next_state <= Sfull;
            ELSIF (regnbok = '0' and 
                   reg4free = '0') THEN 
               next_state <= Serror;
            ELSE
               muxabus <="00";
               next_state <= Sack;
            END IF;
         WHEN Swrodd => 
            latcho <= regnbok and opc_req;
            wr_s <= '1';
            IF (ws_s/=MAX_WS) THEN 
               next_state <= Swsw;
            ELSE
               next_state <= Smaxwsw;
            END IF;
         WHEN Sread => 
            rddata_s <= '1';
            IF (ws_s/=MAX_WS) THEN 
               next_state <= Swsr;
            ELSE
               next_state <= Smaxwsr;
            END IF;
         WHEN Srdodd => 
            rddata_s <= '1';
            IF (ws_s/=MAX_WS) THEN 
               next_state <= Swsr;
            ELSE
               next_state <= Smaxwsr;
            END IF;
         WHEN Swsr => 
            IF (ws_s=MAX_WS-1) THEN 
               next_state <= Smaxwsr;
            ELSE
               next_state <= Swsr;
            END IF;
         WHEN Smaxwsr => 
            latchclr <= '1' ;
            rw_ack<= not rwmem3_s;
            next_state <= Sackr;
         WHEN Sackr => 
            IF (rwmem3_s = '1') THEN 
               muxabus <="10";
               latchrw <= '1';
               next_state <= Srdodd;
            ELSIF (flush_req='1') THEN 
               next_state <= Sflush1;
            ELSIF (irq_req='1' AND opc_req='1') THEN 
               irq_ack<='1';
               next_state <= Sint;
            ELSIF (reg4free = '1' ) THEN 
               muxabus <="00";
                latchrw<='1';
               next_state <= Srdopc;
            ELSIF (flush_coming='1' OR
                   (irq_req='1' AND opc_req='0')) THEN 
               next_state <= Sfull;
            ELSIF (regnbok = '0' and 
                   reg4free = '0') THEN 
               next_state <= Serror;
            ELSE
               muxabus <="00";
               next_state <= Sack;
            END IF;
         WHEN Sflush1 => 
            flush_ack<='1';
            IF (flush_req='0') THEN 
               muxabus<="01";
               next_state <= Sflush2;
            ELSE
               next_state <= Sflush1;
            END IF;
         WHEN Sfull => 
            latcho <= regnbok and opc_req;
            IF (write_req='1') THEN 
               muxabus <="01";
               latchrw <= '1' ;
               next_state <= Swrite;
            ELSIF (read_req='1') THEN 
               muxabus <="01";
               latchrw <= '1' ;
               next_state <= Sread;
            ELSIF (flush_req = '1') THEN 
               next_state <= Sflush1;
            ELSIF (irq_req='1' AND opc_req='1') THEN 
               irq_ack<='1';
               next_state <= Sint;
            ELSIF (reg4free = '1' AND 
                   flush_coming='0' AND
                   irq_req='0') THEN 
               latchrw <= '1' ;
               next_state <= Srdopc;
            ELSIF (regnbok = '0' and 
                   reg4free = '0') THEN 
               next_state <= Serror;
            ELSE
               next_state <= Sfull;
            END IF;
         WHEN Sint => 
            latcho <= opc_req;
            if irq_type="00" then inta1<='1';
            end if;
            irq_ack<='1';
            next_state <= Sintws1;
         WHEN Sintws2 => 
            if irq_type="00" then 
            inta1<='1';
            end if;
            irq_clr <= '1';
            next_state <= Sfull;
         WHEN Sflush2 => 
            latchabus<='1';
            addrplus4<='0'; 
            latchrw <= '1' ;
            muxabus <="01";
            next_state <= Srdopc;
         WHEN Sintws1 => 
            if irq_type="00" then 
            inta1<='1';
            end if;
            next_state <= Sintws2;
         WHEN OTHERS =>
            next_state <= Sreset;
      END CASE;
   END PROCESS nextstate_proc;
 
   -- Concurrent Statements
   -- Clocked output assignments
   biu_status <= biu_status_cld;
   rwmem3_s <= '1' when (w_biufsm_s='1' and oddflag_s='0') else '0';
END fsm;