biufsm_fsm.vhd

Intel微处理器8088的VHDL实现

-------------------------------------------------------------------------------
--  CPU86 - VHDL CPU8088 IP core                                             --
--  Copyright (C) 2005-2008 HT-LAB                                           --
--                                                                           --
--  Contact/bugs : http://www.ht-lab.com/misc/feedback.html                  --
--  Web          : http://www.ht-lab.com                                     --
--                                                                           --
--  CPU86 is released as open-source under the Aladdin Free Public License.  --
--  Contact HT-Lab for commercial applications and/or support contracts.     --
--                                                                           --
--  Full details of the license can be found in the file "cpu86_license.txt" --
--  which is included in the distribution zip file.                          --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;

ENTITY biufsm IS
   PORT( 
      clk          : IN     std_logic;
      flush_coming : IN     std_logic;
      flush_req    : IN     std_logic;
      irq_req      : IN     std_logic;
      irq_type     : IN     std_logic_vector (1 DOWNTO 0);
      opc_req      : IN     std_logic;
      read_req     : IN     std_logic;
      reg1freed    : IN     std_logic;                      -- Delayed version (1 clk) of reg1free
      reg4free     : IN     std_logic;
      regnbok      : IN     std_logic;
      reset        : IN     std_logic;
      w_biufsm_s   : IN     std_logic;
      write_req    : IN     std_logic;
      addrplus4    : OUT    std_logic;
      biu_error    : OUT    std_logic;
      biu_status   : OUT    std_logic_vector (2 DOWNTO 0);
      irq_ack      : OUT    std_logic;
      irq_clr      : OUT    std_logic;
      latchabus    : OUT    std_logic;
      latchclr     : OUT    std_logic;
      latchm       : OUT    std_logic;
      latcho       : OUT    std_logic;
      latchrw      : OUT    std_logic;
      ldposplus1   : OUT    std_logic;
      muxabus      : OUT    std_logic_vector (1 DOWNTO 0);
      rdcode_s     : OUT    std_logic;
      rddata_s     : OUT    std_logic;
      regplus1     : OUT    std_logic;
      rw_ack       : OUT    std_logic;
      wr_s         : OUT    std_logic;
      flush_ack    : BUFFER std_logic;
      inta1        : BUFFER std_logic
   );
END biufsm ;

 
ARCHITECTURE fsm OF biufsm IS

   -- Architecture Declarations
   signal ws_s : std_logic_vector(WS_WIDTH-1 downto 0);
   signal oddflag_s  : std_logic;
   signal rwmem3_s : std_logic; -- Misaligned Read/Write cycle

   TYPE STATE_TYPE IS (
      Sreset,
      Sws,
      Smaxws,
      Sack,
      Srdopc,
      Serror,
      Swrite,
      Swsw,
      Smaxwsw,
      Sackw,
      Swrodd,
      Sread,
      Srdodd,
      Swsr,
      Smaxwsr,
      Sackr,
      Sflush1,
      Sfull,
      Sint,
      Sintws2,
      Sflush2,
      Sintws1
   );
 
   -- State vector declaration
   ATTRIBUTE state_vector : string;
   ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state";

   -- Declare current and next state signals
   SIGNAL current_state : STATE_TYPE;
   SIGNAL next_state : STATE_TYPE;

   -- Declare any pre-registered internal signals
   SIGNAL biu_error_int : std_logic ;
   SIGNAL biu_status_cld : std_logic_vector (2 DOWNTO 0);

BEGIN

   -----------------------------------------------------------------
   clocked_proc : PROCESS ( 
      clk,
      reset
   )
   -----------------------------------------------------------------
   BEGIN
      IF (reset = '1') THEN
         current_state <= Sreset;
         -- Default Reset Values
         biu_error <= '0';
         biu_status_cld <= "011";
         oddflag_s <= '0';
         ws_s <= (others=>'0');
      ELSIF (clk'EVENT AND clk = '1') THEN
         current_state <= next_state;
         -- Registered output assignments
         biu_error <= biu_error_int;
         -- Default Assignment To Internals
         ws_s <= (others=>'0');

         -- Combined Actions
         CASE current_state IS
            WHEN Sreset => 
               biu_status_cld<="000";
            WHEN Sws => 
               ws_s <= ws_s + '1';
               IF (flush_req = '1') THEN 
                  biu_status_cld<="011";
               END IF;
            WHEN Smaxws => 
               IF (flush_req = '1') THEN 
                  biu_status_cld<="011";
               END IF;
            WHEN Sack => 
               oddflag_s<='0';
               IF (write_req = '1') THEN 
                  biu_status_cld<="010";
               ELSIF (read_req = '1') THEN 
                  biu_status_cld<="001";
               ELSIF (flush_req = '1') THEN 
                  biu_status_cld<="011";
               ELSIF (irq_req='1' AND opc_req='1') THEN 
                  biu_status_cld<="100";
               ELSIF (reg4free = '1' AND
                      flush_coming='0' AND
                      irq_req='0') THEN 
                  biu_status_cld<="000";
               ELSIF (regnbok = '0' and 
                      reg4free = '0') THEN 
               ELSE
                  biu_status_cld<="011";
               END IF;
            WHEN Srdopc => 
               ws_s <= (others=>'0');
               IF (flush_req = '1') THEN 
                  biu_status_cld<="011";
               END IF;
            WHEN Swrite => 
               ws_s <= (others=>'0');
               oddflag_s<='0';
            WHEN Swsw => 
               ws_s <= ws_s + '1';
            WHEN Sackw => 
               IF (rwmem3_s = '1') THEN 
               ELSIF (flush_req = '1') THEN 
                  biu_status_cld<="011";
               ELSIF (irq_req='1' AND opc_req='1') THEN 
                  biu_status_cld<="100";
               ELSIF (reg4free = '1' ) THEN 
                  biu_status_cld<="000";
               ELSIF (flush_coming='1' OR
                      (irq_req='1' AND opc_req='0')) THEN 
                  biu_status_cld<="011";
               END IF;
            WHEN Swrodd => 
               ws_s <= (others=>'0');
               oddflag_s<='1';
            WHEN Sread => 
               ws_s <= (others=>'0');
               oddflag_s<='0';
            WHEN Srdodd => 
               ws_s <= (others=>'0');
               oddflag_s<='1';
            WHEN Swsr => 
               ws_s <= ws_s + '1';
            WHEN Sackr => 
               IF (rwmem3_s = '1') THEN 
               ELSIF (flush_req='1') THEN 
                  biu_status_cld<="011";
               ELSIF (irq_req='1' AND opc_req='1') THEN 
                  biu_status_cld<="100";
               ELSIF (reg4free = '1' ) THEN 
                  biu_status_cld<="000";
               ELSIF (flush_coming='1' OR
                      (irq_req='1' AND opc_req='0')) THEN 
                  biu_status_cld<="011";
               END IF;
            WHEN Sfull => 
               IF (write_req='1') THEN 
                  biu_status_cld<="010";
               ELSIF (read_req='1') THEN 
                  biu_status_cld<="001";
               ELSIF (flush_req = '1') THEN 
                  biu_status_cld<="011";
               ELSIF (irq_req='1' AND opc_req='1') THEN 
                  biu_status_cld<="100";
               ELSIF (reg4free = '1' AND 
                      flush_coming='0' AND
                      irq_req='0') THEN 
                  biu_status_cld<="000";
               END IF;
            WHEN Sintws2 => 
               biu_status_cld<="011";
            WHEN Sflush2 => 
               biu_status_cld<="000";
            WHEN OTHERS =>
               NULL;
         END CASE;
      END IF;
   END PROCESS clocked_proc;
 
   -----------------------------------------------------------------
   nextstate_proc : PROCESS ( 
      current_state,
      flush_coming,
      flush_req,
      irq_req,
      irq_type,
      opc_req,
      read_req,
      reg1freed,
      reg4free,
      regnbok,
      rwmem3_s,
      write_req,
      ws_s
   )
   -----------------------------------------------------------------
   BEGIN
      -- Default Assignment
      addrplus4 <= '0';
      biu_error_int <= '0';
      irq_ack <= '0';