📄 cpu86_struct.vhd
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-- -----------------------------------------------------------------------------
-- --
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2005-2008 HT-LAB --
-- --
-- Contact/bugs : cpu86@ht-lab.com --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the Aladdin Free Public License. --
-- Contact HT-Lab for commercial applications and/or support contracts. --
-- --
-- -----------------------------------------------------------------------------
-- Aladdin Free Public License --
-- (Version 9, September 18, 2000) --
-- Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000 Aladdin Enterprises, --
-- Menlo Park, California, U.S.A. All rights reserved. --
-- --
-- NOTE: This License is not the same as any of the GNU Licenses published --
-- by the Free Software Foundation. Its terms are substantially different --
-- from those of the GNU Licenses.If you are familiar with the GNU Licenses --
-- please read this license with extra care. --
-- Aladdin Enterprises hereby grants to anyone the permission to apply this --
-- License to their own work, as long as the entire License ( including the --
-- above notices and this paragraph) is copied with no changes, additions, --
-- or deletions except for changing the first paragraph of Section 0 to --
-- include a suitable description of the work to which the license is being --
-- applied and of the person or entity that holds the copyright in the work,--
-- and,if the License is being applied to a work created in a country other --
-- than the United States, replacing the first paragraph of Section 6 with --
-- an appropriate reference to the laws of the appropriate country. --
-- --
-- This License is not an Open Source license: among other things,it places --
-- restrictions on distribution of the Program, specifically including sale --
-- of the Program. While Aladdin Enterprises respects and supports the --
-- philosophy of the Open Source Definition, and shares the desire of the --
-- GNU project to keep licensed software freely redistributable in both --
-- source and object form, we feel that Open Source licenses unfairly --
-- prevent developers of useful software from being compensated propor- --
-- tionately when others profit financially from their work. This License --
-- attempts to ensure that those who receive, redistribute, and contribute --
-- to the licensed Program according to the Open Source and Free Software --
-- philosophies have the right to do so, while retaining for the developers --
-- of the Program the power to make those who use the Program to enhance --
-- the value of commercial products pay for the privilege of doing so. --
-- --
-- -----------------------------------------------------------------------------
-- 0. Subject Matter --
-- --
-- This License applies to the intellectual property core known as "CPU86". --
-- The "Program", below, refers to such a core.The Program is a copyrighted --
-- work whose copyright is held by Hans Tiggeler of HT-Lab located in the --
-- United Kingdom (the "Licensor"). --
-- --
-- A "work based on the Program" means either the Program or any derivative --
-- work of the Program, as defined in the United States Copyright Act of --
-- 1976, such as a translation or a modification. --
-- --
-- BY MODIFYING OR DISTRIBUTING THE PROGRAM (OR ANY WORK BASED ON THE --
-- PROGRAM), YOU INDICATE YOUR ACCEPTANCE OF THIS LICENSE TO DO SO, AND ALL --
-- ITS TERMS AND CONDITIONS FOR COPYING, DISTRIBUTING OR MODIFYING THE --
-- PROGRAM OR WORKS BASED ON IT. NOTHING OTHER THAN THIS LICENSE GRANTS YOU --
-- PERMISSION TO MODIFY OR DISTRIBUTE THE PROGRAM OR ITS DERIVATIVE WORKS. --
-- THESE ACTIONS ARE PROHIBITED BY LAW.IF YOU DO NOT ACCEPT THESE TERMS AND --
-- CONDITIONS, DO NOT MODIFY OR DISTRIBUTE THE PROGRAM. --
-- --
-- Full details of the license can be found in the file "cpu86_license.txt" --
-- which is included in the distribution zip file. --
-- -----------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 17 May 2008 0.75 H. Tiggeler Ported some bug fixes back from the --
-- commercial HTL8086 to the CPU86. --
-- 30 Dec 2007 0.71 H. Tiggeler Fixed Trace (I broke it in ver 0.69)--
-- 09 Dec 2007 0.70 H. Tiggeler Updated for Xilinx XST synthesizer --
-- 07 Oct 2006 0.69 H. Tiggeler Fixed INTA/SHL logic as reported by --
-- R. Kilgore --
-- 07 Oct 2006 0.69 R. Kilgore Fixed RD strobe during INTA --
-- 23 Nov 2006 0.68 H. Tiggeler Fixed INTA vector read --
-- 29 Dec 2005 0.67 H. Tiggeler First web version --
-- -----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;
ENTITY cpu86 IS
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END cpu86 ;
ARCHITECTURE struct OF cpu86 IS
-- Internal signal declarations
SIGNAL abus_out : std_logic_vector(19 DOWNTO 0);
SIGNAL biu_error : std_logic;
SIGNAL clrop : std_logic;
SIGNAL dbusdp_out : std_logic_vector(15 DOWNTO 0);
SIGNAL decode_state : std_logic;
SIGNAL flush_ack : std_logic;
SIGNAL flush_coming : std_logic;
SIGNAL flush_req : std_logic;
SIGNAL instr : instruction_type;
SIGNAL inta1 : std_logic;
SIGNAL intack : std_logic;
SIGNAL iomem : std_logic;
SIGNAL irq_blocked : std_logic;
SIGNAL irq_req : std_logic;
SIGNAL latcho : std_logic;
SIGNAL mdbus_out : std_logic_vector(15 DOWNTO 0);
SIGNAL opc_req : std_logic;
SIGNAL path : path_in_type;
SIGNAL proc_error : std_logic;
SIGNAL read_req : std_logic;
SIGNAL reset : std_logic;
SIGNAL rw_ack : std_logic;
SIGNAL status : status_out_type;
SIGNAL word : std_logic;
SIGNAL write_req : std_logic;
SIGNAL wrpath : write_in_type;
-- Component Declarations
COMPONENT biu
PORT (
abusdp_in : IN std_logic_vector (19 DOWNTO 0);
clk : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
dbusdp_in : IN std_logic_vector (15 DOWNTO 0);
decode_state : IN std_logic ;
flush_coming : IN std_logic ;
flush_req : IN std_logic ;
intack : IN std_logic ;
intr : IN std_logic ;
iomem : IN std_logic ;
irq_block : IN std_logic ;
nmi : IN std_logic ;
opc_req : IN std_logic ;
read_req : IN std_logic ;
reset : IN std_logic ;
status : IN status_out_type ;
word : IN std_logic ;
write_req : IN std_logic ;
abus : OUT std_logic_vector (19 DOWNTO 0);
biu_error : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
flush_ack : OUT std_logic ;
instr : OUT instruction_type ;
inta : OUT std_logic ;
inta1 : OUT std_logic ;
iom : OUT std_logic ;
irq_req : OUT std_logic ;
latcho : OUT std_logic ;
mdbus_out : OUT std_logic_vector (15 DOWNTO 0);
rdn : OUT std_logic ;
rw_ack : OUT std_logic ;
wran : OUT std_logic ;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT datapath
PORT (
clk : IN std_logic ;
clrop : IN std_logic ;
instr : IN instruction_type ;
iomem : IN std_logic ;
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
path : IN path_in_type ;
reset : IN std_logic ;
wrpath : IN write_in_type ;
abusdp_out : OUT std_logic_vector (19 DOWNTO 0);
dbusdp_out : OUT std_logic_vector (15 DOWNTO 0);
status : OUT status_out_type
);
END COMPONENT;
COMPONENT proc
PORT (
clk : IN std_logic ;
flush_ack : IN std_logic ;
instr : IN instruction_type ;
inta1 : IN std_logic ;
irq_req : IN std_logic ;
latcho : IN std_logic ;
reset : IN std_logic ;
rw_ack : IN std_logic ;
status : IN status_out_type ;
clrop : OUT std_logic ;
decode_state : OUT std_logic ;
flush_coming : OUT std_logic ;
flush_req : OUT std_logic ;
intack : OUT std_logic ;
iomem : OUT std_logic ;
irq_blocked : OUT std_logic ;
opc_req : OUT std_logic ;
path : OUT path_in_type ;
proc_error : OUT std_logic ;
read_req : OUT std_logic ;
word : OUT std_logic ;
write_req : OUT std_logic ;
wrpath : OUT write_in_type
);
END COMPONENT;
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 RES
-- eb1 2
-- synchronous reset
-- Internal use active high, external use active low
-- Async Asserted, sync negated
process (clk, por)
begin
if por='1' then
reset <= '1';
resoutn <= '0';
elsif rising_edge(clk) then
reset <= '0';
resoutn <= '1';
end if;
end process;
-- HDL Embedded Text Block 3 Copyright
-- Copyright 3
-- pragma translate_off
process
begin
wait until falling_edge (reset);
report "********** CPU86 ver0.75";
report "********** Copyright (c) 2003-2008 HT Lab WWW.HT-LAB.COM";
wait;
end process;
-- pragma translate_on
-- ModuleWare code(v1.9) for instance 'I0' of 'or'
cpuerror <= proc_error OR biu_error;
-- Instance port mappings.
cpubiu : biu
PORT MAP (
abusdp_in => abus_out,
clk => clk,
dbus_in => dbus_in,
dbusdp_in => dbusdp_out,
decode_state => decode_state,
flush_coming => flush_coming,
flush_req => flush_req,
intack => intack,
intr => intr,
iomem => iomem,
irq_block => irq_blocked,
nmi => nmi,
opc_req => opc_req,
read_req => read_req,
reset => reset,
status => status,
word => word,
write_req => write_req,
abus => abus,
biu_error => biu_error,
dbus_out => dbus_out,
flush_ack => flush_ack,
instr => instr,
inta => inta,
inta1 => inta1,
iom => iom,
irq_req => irq_req,
latcho => latcho,
mdbus_out => mdbus_out,
rdn => rdn,
rw_ack => rw_ack,
wran => wran,
wrn => wrn
);
cpudpath : datapath
PORT MAP (
clk => clk,
clrop => clrop,
instr => instr,
iomem => iomem,
mdbus_in => mdbus_out,
path => path,
reset => reset,
wrpath => wrpath,
abusdp_out => abus_out,
dbusdp_out => dbusdp_out,
status => status
);
cpuproc : proc
PORT MAP (
clk => clk,
flush_ack => flush_ack,
instr => instr,
inta1 => inta1,
irq_req => irq_req,
latcho => latcho,
reset => reset,
rw_ack => rw_ack,
status => status,
clrop => clrop,
decode_state => decode_state,
flush_coming => flush_coming,
flush_req => flush_req,
intack => intack,
iomem => iomem,
irq_blocked => irq_blocked,
opc_req => opc_req,
path => path,
proc_error => proc_error,
read_req => read_req,
word => word,
write_req => write_req,
wrpath => wrpath
);
END struct;
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