irda_uart.vhd

adc转换功能的vhdl源码

-- *******************************************************************
-- 
-- Owner:	Xilinx Inc.
-- File:  	irda_uart.vhd
--
-- Purpose: 	Main IrDA and UART instantiation.  This interface
-- 		interprets UART data read/write protocol and
-- 		controls the IrDA signals to light emitting diodes.
--
-- Created:	VHDL code generated by Visual HDL 8-15-01
--  
-- *******************************************************************

 
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_MISC.all;
use ieee.STD_LOGIC_UNSIGNED.all;

library work;
use work.pkg_util.all; 
 
entity irda_uart is
  port (
        data 		: inout STD_LOGIC_VECTOR (7 downto 0);
        mclkx16 	: in 	STD_LOGIC;
        write 		: in 	STD_LOGIC;
        read 		: in 	STD_LOGIC;
        reset 		: in 	STD_LOGIC;
        parity_error 	: out 	STD_LOGIC;
        framing_error 	: out 	STD_LOGIC;
        overrun 	: out 	STD_LOGIC;
        rxrdy 		: out 	STD_LOGIC;
        txrdy 		: out 	STD_LOGIC;
        irtxd 		: out 	STD_LOGIC;
        irrxd 		: in 	STD_LOGIC
        );
end irda_uart;
 

architecture behavior of irda_uart is
 
  component uart
      port (
            mclkx16 	: in STD_LOGIC := 'Z';
            reset 	: in STD_LOGIC := 'Z';
            read 	: in STD_LOGIC := 'Z';
            write 	: in STD_LOGIC := 'Z';
            data 	: inout STD_LOGIC_VECTOR (7 downto 0) := "ZZZZZZZZ";
            sin 	: in STD_LOGIC := 'Z';
            sout 	: out STD_LOGIC := 'Z';
            rxrdy 	: out STD_LOGIC := 'Z';
            txrdy 	: out STD_LOGIC := 'Z';
            parity_error : out STD_LOGIC := 'Z';
            framing_error : out STD_LOGIC := 'Z';
            overrun 	: out STD_LOGIC := 'Z'
            );	
  end component;
  
  component sirendec
      port (
            clk16x 	: in STD_LOGIC := 'Z';
            irrxd 	: in STD_LOGIC := 'Z';
            nrcven 	: in STD_LOGIC := 'Z';
            rxd 	: out STD_LOGIC;
            txd 	: in STD_LOGIC := 'Z';
            irtxd 	: out STD_LOGIC := 'Z'
            );
  end component;
  
  signal rx 	: STD_LOGIC;   --  Serial data to connect UART & IrDA module
  signal tx 	: STD_LOGIC;
  signal nrcven : STD_LOGIC := 'Z';
  
begin
 
  nrcven <= not(reset);
 
  --  Instatiate UART module
  uart_module: uart
    port map (
              mclkx16,
              reset,
              read,
              write,
              data,
              rx,
              tx,
              rxrdy,
              txrdy,
              parity_error,
              framing_error,
              overrun );
 
  --  Instatiate Encoder/Decoder
  irda_module: sirendec
    port map (
              mclkx16,
              irrxd,
              nrcven,
              rx,
              tx,
              irtxd );
 
end ;