irda_uart_timesim.vhd

adc转换功能的vhdl源码

    );
  read_II_UIM_7 : X_BUF
    port map (
      I => read,
      O => read_II_UIM
    );
  read_II_FCLK_8 : X_BUF
    port map (
      I => read,
      O => read_II_FCLK
    );
  data_0_MC_BUFOE : X_BUF
    port map (
      I => FOOBAR5_ctinst_0,
      O => data_0_MC_BUFOE_OUT
    );
  uart_module_rx_rhr_0_Q : X_BUF
    port map (
      I => uart_module_rx_rhr_0_MC_Q,
      O => uart_module_rx_rhr(0)
    );
  uart_module_rx_rhr_0_MC_R_OR_PRLD_9 : X_OR2
    port map (
      I0 => FOOBAR2_ctinst_7,
      I1 => PRLD,
      O => uart_module_rx_rhr_0_MC_R_OR_PRLD
    );
  uart_module_rx_rhr_0_MC_REG : X_FF
    port map (
      I => uart_module_rx_rhr_0_MC_D,
      CE => FOOBAR1_ctinst_4,
      CLK => mclkx16_II_FCLK,
      SET => GND,
      RST => uart_module_rx_rhr_0_MC_R_OR_PRLD,
      O => uart_module_rx_rhr_0_MC_Q
    );
  FOOBAR2_ctinst_0_10 : X_AND2
    port map (
      I0 => N_PZ_459,
      I1 => N_PZ_459,
      O => NlwInverterSignal_FOOBAR2_ctinst_0_OUT
    );
  FOOBAR2_ctinst_4_11 : X_AND2
    port map (
      I0 => uart_module_tx_N254,
      I1 => uart_module_tx_N254,
      O => NlwInverterSignal_FOOBAR2_ctinst_4_OUT
    );
  FOOBAR2_ctinst_5_12 : X_AND2
    port map (
      I0 => uart_module_rx_rxclk,
      I1 => uart_module_rx_rxclk,
      O => FOOBAR2_ctinst_5
    );
  FOOBAR2_ctinst_7_13 : X_AND2
    port map (
      I0 => reset_II_UIM,
      I1 => reset_II_UIM,
      O => FOOBAR2_ctinst_7
    );
  N_PZ_459_14 : X_BUF
    port map (
      I => N_PZ_459_MC_Q,
      O => N_PZ_459
    );
  N_PZ_459_MC_REG : X_BUF
    port map (
      I => N_PZ_459_MC_D,
      O => N_PZ_459_MC_Q
    );
  N_PZ_459_MC_D1_PT_0_15 : X_AND2
    port map (
      I0 => reset_II_UIM,
      I1 => reset_II_UIM,
      O => N_PZ_459_MC_D1_PT_0
    );
  N_PZ_459_MC_D1_16 : X_OR2
    port map (
      I0 => N_PZ_459_MC_D1_PT_0,
      I1 => N_PZ_459_MC_D1_PT_0,
      O => N_PZ_459_MC_D1
    );
  N_PZ_459_MC_D2_17 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => N_PZ_459_MC_D2
    );
  N_PZ_459_MC_XOR : X_XOR2
    port map (
      I0 => NlwInverterSignal_N_PZ_459_MC_XOR_IN0,
      I1 => N_PZ_459_MC_D2,
      O => N_PZ_459_MC_D
    );
  reset_II_UIM_18 : X_BUF
    port map (
      I => reset,
      O => reset_II_UIM
    );
  xPUP_0_II_UIM_19 : X_BUF
    port map (
      I => xPUP_0,
      O => xPUP_0_II_UIM
    );
  uart_module_tx_N254_20 : X_BUF
    port map (
      I => uart_module_tx_N254_MC_Q,
      O => uart_module_tx_N254
    );
  uart_module_tx_N254_MC_REG : X_BUF
    port map (
      I => uart_module_tx_N254_MC_D,
      O => uart_module_tx_N254_MC_Q
    );
  uart_module_tx_N254_MC_D1_21 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => uart_module_tx_N254_MC_D1
    );
  uart_module_tx_N254_MC_D2_PT_0_22 : X_AND2
    port map (
      I0 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_0_IN0,
      I1 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_0_IN1,
      O => uart_module_tx_N254_MC_D2_PT_0
    );
  uart_module_tx_N254_MC_D2_PT_1_23 : X_AND2
    port map (
      I0 => uart_module_tx_write2,
      I1 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_1_IN1,
      O => uart_module_tx_N254_MC_D2_PT_1
    );
  uart_module_tx_N254_MC_D2_PT_2_24 : X_AND16
    port map (
      I0 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN0,
      I1 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN1,
      I2 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN2,
      I3 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN3,
      I4 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN4,
      I5 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN5,
      I6 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN6,
      I7 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN7,
      I8 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN8,
      I9 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN9,
      I10 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN10,
      I11 => VCC,
      I12 => VCC,
      I13 => VCC,
      I14 => VCC,
      I15 => VCC,
      O => uart_module_tx_N254_MC_D2_PT_2
    );
  uart_module_tx_N254_MC_D2_PT_3_25 : X_AND16
    port map (
      I0 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN0,
      I1 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN1,
      I2 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN2,
      I3 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN3,
      I4 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN4,
      I5 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN5,
      I6 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN6,
      I7 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN7,
      I8 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN8,
      I9 => NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN9,
      I10 => uart_module_tx_write2,
      I11 => VCC,
      I12 => VCC,
      I13 => VCC,
      I14 => VCC,
      I15 => VCC,
      O => uart_module_tx_N254_MC_D2_PT_3
    );
  uart_module_tx_N254_MC_D2_26 : X_OR4
    port map (
      I0 => uart_module_tx_N254_MC_D2_PT_0,
      I1 => uart_module_tx_N254_MC_D2_PT_1,
      I2 => uart_module_tx_N254_MC_D2_PT_2,
      I3 => uart_module_tx_N254_MC_D2_PT_3,
      O => uart_module_tx_N254_MC_D2
    );
  uart_module_tx_N254_MC_XOR : X_XOR2
    port map (
      I0 => uart_module_tx_N254_MC_D1,
      I1 => uart_module_tx_N254_MC_D2,
      O => uart_module_tx_N254_MC_D
    );
  uart_module_tx_write1_27 : X_BUF
    port map (
      I => uart_module_tx_write1_MC_Q,
      O => uart_module_tx_write1
    );
  uart_module_tx_write1_MC_REG : X_FF
    port map (
      I => uart_module_tx_write1_MC_D,
      CE => VCC,
      CLK => mclkx16_II_FCLK,
      SET => FOOBAR2_ctinst_7,
      RST => PRLD,
      O => uart_module_tx_write1_MC_Q
    );
  uart_module_tx_write1_MC_D1_PT_0_28 : X_AND2
    port map (
      I0 => write_II_UIM,
      I1 => write_II_UIM,
      O => uart_module_tx_write1_MC_D1_PT_0
    );
  uart_module_tx_write1_MC_D1_29 : X_OR2
    port map (
      I0 => uart_module_tx_write1_MC_D1_PT_0,
      I1 => uart_module_tx_write1_MC_D1_PT_0,
      O => uart_module_tx_write1_MC_D1
    );
  uart_module_tx_write1_MC_D2_30 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => uart_module_tx_write1_MC_D2
    );
  uart_module_tx_write1_MC_XOR : X_XOR2
    port map (
      I0 => uart_module_tx_write1_MC_D1,
      I1 => uart_module_tx_write1_MC_D2,
      O => uart_module_tx_write1_MC_D
    );
  write_II_UIM_31 : X_BUF
    port map (
      I => write,
      O => write_II_UIM
    );
  write_II_FCLK_32 : X_BUF
    port map (
      I => write,
      O => write_II_FCLK
    );
  mclkx16_II_FCLK_33 : X_BUF
    port map (
      I => mclkx16,
      O => mclkx16_II_FCLK
    );
  uart_module_tx_txdone1_34 : X_BUF
    port map (
      I => uart_module_tx_txdone1_MC_Q,
      O => uart_module_tx_txdone1
    );
  uart_module_tx_txdone1_MC_REG : X_FF
    port map (
      I => uart_module_tx_txdone1_MC_D,
      CE => VCC,
      CLK => mclkx16_II_FCLK,
      SET => FOOBAR2_ctinst_7,
      RST => PRLD,
      O => uart_module_tx_txdone1_MC_Q
    );
  uart_module_tx_txdone1_MC_D1_PT_0_35 : X_AND16
    port map (
      I0 => NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN0,
      I1 => NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN1,
      I2 => NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN2,
      I3 => NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN3,
      I4 => NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN4,
      I5 => NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN5,
      I6 => NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN6,
      I7 => NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN7,
      I8 => NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN8,
      I9 => NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN9,
      I10 => VCC,
      I11 => VCC,
      I12 => VCC,
      I13 => VCC,
      I14 => VCC,
      I15 => VCC,
      O => uart_module_tx_txdone1_MC_D1_PT_0
    );
  uart_module_tx_t