irda_uart_timesim.vhd

adc转换功能的vhdl源码

  signal NlwInverterSignal_uart_module_rx_rxcnt_1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_1_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_1_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_1_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_2_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_2_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_2_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_2_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_2_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_trigctl_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_2_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_N73_MC_D2_PT_2_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_1_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_1_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_1_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_1_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_1_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_1_MC_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_1_MC_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_1_MC_D2_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_2_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_2_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_2_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_2_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_2_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_2_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_2_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_2_MC_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_2_MC_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_2_MC_D2_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_3_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_3_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_3_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_3_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_3_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_3_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_3_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_3_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_3_MC_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_3_MC_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_3_MC_D2_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_4_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_4_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_4_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_4_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_4_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_4_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_4_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_4_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_4_MC_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_4_MC_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_4_MC_D2_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_5_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_5_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_5_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_5_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_5_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_5_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_5_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_5_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_5_MC_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_5_MC_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_5_MC_D2_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_6_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_6_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_6_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_6_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_6_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_6_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_6_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_6_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_6_MC_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_6_MC_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_6_MC_D2_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_7_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_7_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_7_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_7_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_7_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_7_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_7_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_7_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_7_MC_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_7_MC_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_7_MC_D2_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag1_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag1_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag1_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag1_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag1_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag1_MC_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag1_MC_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag1_MC_D2_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag2_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag2_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag2_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag2_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag2_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag2_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag2_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag2_MC_D1_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag2_MC_D1_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag2_MC_D1_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tag2_MC_D1_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_txrdy_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_txrdy_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txparity_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txparity_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txparity_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txparity_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txparity_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txparity_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txparity_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txparity_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txparity_MC_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txparity_MC_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txparity_MC_D2_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_255_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_255_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_255_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_rxrdy_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_rxrdy_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txclk_MC_CE_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txclk_MC_CE_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txclk_MC_CE_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txclk_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_cnt_0_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_0_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_0_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_0_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_0_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_0_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_0_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_0_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_0_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_0_MC_D2_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_0_MC_D2_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_tsr_0_MC_D2_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rhr_3_MC_CE_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rhr_3_MC_CE_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rhr_4_MC_CE_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rhr_4_MC_CE_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rhr_5_MC_CE_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rhr_5_MC_CE_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rhr_6_MC_CE_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rhr_6_MC_CE_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rhr_7_MC_CE_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rhr_7_MC_CE_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_framing_error_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_framing_error_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_framing_error_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_framing_error_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irtxd_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_irtxd_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_irtxd_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irtxd_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_count4bit_0_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_overrun_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_overrun_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_overrun_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_parity_error_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_parity_error_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_paritygen_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_paritygen_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_paritygen_MC_XOR_IN0 : STD_LOGIC; 
  signal uart_module_rx_rhr : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal uart_module_tx_tsr : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal uart_module_rx_rsr : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal uart_module_rx_rxcnt : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal uart_module_tx_thr : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal uart_module_tx_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal irda_module_count4bit : STD_LOGIC_VECTOR ( 3 downto 0 ); 
begin
  data_0_Q : X_TRI
    port map (
      I => data_0_MC_Q,
      CTL => data_0_MC_OE,
      O => data(0)
    );
  data_0_MC_Q_0 : X_BUF
    port map (
      I => data_0_MC_Q_tsim_ireg_Q,
      O => data_0_MC_Q
    );
  data_0_MC_REG : X_LATCHE
    port map (
      I => data_0_MC_D,
      GE => VCC,
      CLK => read_II_FCLK_tsimcreated_inv_Q,
      SET => GND,
      RST => PRLD,
      O => data_0_MC_Q_tsim_ireg_Q
    );
  read_II_FCLK_tsimcreated_inv_Q_1 : X_INV
    port map (
      I => read_II_FCLK,
      O => read_II_FCLK_tsimcreated_inv_Q
    );
  VCC_ONE : X_ONE
    port map (
      O => VCC
    );
  data_0_MC_D1_PT_0_2 : X_AND2
    port map (
      I0 => uart_module_rx_rhr(0),
      I1 => uart_module_rx_rhr(0),
      O => data_0_MC_D1_PT_0
    );
  data_0_MC_D1_3 : X_OR2
    port map (
      I0 => data_0_MC_D1_PT_0,
      I1 => data_0_MC_D1_PT_0,
      O => data_0_MC_D1
    );
  GND_ZERO : X_ZERO
    port map (
      O => GND
    );
  data_0_MC_D2_4 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => data_0_MC_D2
    );
  data_0_MC_XOR : X_XOR2
    port map (
      I0 => data_0_MC_D1,
      I1 => data_0_MC_D2,
      O => data_0_MC_D
    );
  data_0_MC_OE_5 : X_BUF
    port map (
      I => data_0_MC_BUFOE_OUT,
      O => data_0_MC_OE
    );
  FOOBAR5_ctinst_0_6 : X_AND2
    port map (
      I0 => read_II_UIM,
      I1 => read_II_UIM,
      O => NlwInverterSignal_FOOBAR5_ctinst_0_OUT