irda_uart_timesim.vhd

adc转换功能的vhdl源码

  signal uart_module_rx_rhr_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_rx_rhr_2_MC_D : STD_LOGIC; 
  signal uart_module_rx_rhr_2_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_2_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rhr_2_MC_D2 : STD_LOGIC; 
  signal data_3_MC_Q : STD_LOGIC; 
  signal data_3_MC_OE : STD_LOGIC; 
  signal data_3_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_3_MC_D : STD_LOGIC; 
  signal data_3_MC_D1_PT_0 : STD_LOGIC; 
  signal data_3_MC_D1 : STD_LOGIC; 
  signal data_3_MC_D2 : STD_LOGIC; 
  signal data_3_MC_BUFOE_OUT : STD_LOGIC; 
  signal uart_module_rx_rhr_3_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rhr_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_rx_rhr_3_MC_D : STD_LOGIC; 
  signal uart_module_rx_rhr_3_MC_CE : STD_LOGIC; 
  signal uart_module_rx_rhr_3_MC_CE_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_3_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_3_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rhr_3_MC_D2 : STD_LOGIC; 
  signal data_4_MC_Q : STD_LOGIC; 
  signal data_4_MC_OE : STD_LOGIC; 
  signal data_4_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_4_MC_D : STD_LOGIC; 
  signal data_4_MC_D1_PT_0 : STD_LOGIC; 
  signal data_4_MC_D1 : STD_LOGIC; 
  signal data_4_MC_D2 : STD_LOGIC; 
  signal data_4_MC_BUFOE_OUT : STD_LOGIC; 
  signal uart_module_rx_rhr_4_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rhr_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_rx_rhr_4_MC_D : STD_LOGIC; 
  signal uart_module_rx_rhr_4_MC_CE : STD_LOGIC; 
  signal uart_module_rx_rhr_4_MC_CE_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_4_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_4_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rhr_4_MC_D2 : STD_LOGIC; 
  signal data_5_MC_Q : STD_LOGIC; 
  signal data_5_MC_OE : STD_LOGIC; 
  signal data_5_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_5_MC_D : STD_LOGIC; 
  signal data_5_MC_D1_PT_0 : STD_LOGIC; 
  signal data_5_MC_D1 : STD_LOGIC; 
  signal data_5_MC_D2 : STD_LOGIC; 
  signal data_5_MC_BUFOE_OUT : STD_LOGIC; 
  signal uart_module_rx_rhr_5_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rhr_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_rx_rhr_5_MC_D : STD_LOGIC; 
  signal uart_module_rx_rhr_5_MC_CE : STD_LOGIC; 
  signal uart_module_rx_rhr_5_MC_CE_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_5_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_5_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rhr_5_MC_D2 : STD_LOGIC; 
  signal data_6_MC_Q : STD_LOGIC; 
  signal data_6_MC_OE : STD_LOGIC; 
  signal data_6_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_6_MC_D : STD_LOGIC; 
  signal data_6_MC_D1_PT_0 : STD_LOGIC; 
  signal data_6_MC_D1 : STD_LOGIC; 
  signal data_6_MC_D2 : STD_LOGIC; 
  signal data_6_MC_BUFOE_OUT : STD_LOGIC; 
  signal uart_module_rx_rhr_6_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rhr_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_rx_rhr_6_MC_D : STD_LOGIC; 
  signal uart_module_rx_rhr_6_MC_CE : STD_LOGIC; 
  signal uart_module_rx_rhr_6_MC_CE_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_6_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_6_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rhr_6_MC_D2 : STD_LOGIC; 
  signal data_7_MC_Q : STD_LOGIC; 
  signal data_7_MC_OE : STD_LOGIC; 
  signal data_7_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_7_MC_D : STD_LOGIC; 
  signal data_7_MC_D1_PT_0 : STD_LOGIC; 
  signal data_7_MC_D1 : STD_LOGIC; 
  signal data_7_MC_D2 : STD_LOGIC; 
  signal data_7_MC_BUFOE_OUT : STD_LOGIC; 
  signal uart_module_rx_rhr_7_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rhr_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_rx_rhr_7_MC_D : STD_LOGIC; 
  signal uart_module_rx_rhr_7_MC_CE : STD_LOGIC; 
  signal uart_module_rx_rhr_7_MC_CE_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_7_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_7_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rhr_7_MC_D2 : STD_LOGIC; 
  signal framing_error_MC_Q : STD_LOGIC; 
  signal framing_error_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal framing_error_MC_R_OR_PRLD : STD_LOGIC; 
  signal framing_error_MC_D : STD_LOGIC; 
  signal framing_error_MC_D1 : STD_LOGIC; 
  signal framing_error_MC_UIM : STD_LOGIC; 
  signal framing_error_MC_D2_PT_0 : STD_LOGIC; 
  signal framing_error_MC_D2_PT_1 : STD_LOGIC; 
  signal framing_error_MC_D2_PT_2 : STD_LOGIC; 
  signal framing_error_MC_D2 : STD_LOGIC; 
  signal irtxd_MC_Q : STD_LOGIC; 
  signal irtxd_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal irtxd_MC_R_OR_PRLD : STD_LOGIC; 
  signal irtxd_MC_D : STD_LOGIC; 
  signal irtxd_MC_D1 : STD_LOGIC; 
  signal irtxd_MC_UIM : STD_LOGIC; 
  signal irtxd_MC_D2_PT_0 : STD_LOGIC; 
  signal irtxd_MC_D2_PT_1 : STD_LOGIC; 
  signal irtxd_MC_D2 : STD_LOGIC; 
  signal irtxd_MC_D_TFF : STD_LOGIC; 
  signal irda_module_count4bit_0_MC_Q : STD_LOGIC; 
  signal irda_module_count4bit_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal irda_module_count4bit_0_MC_D : STD_LOGIC; 
  signal irda_module_count4bit_0_MC_D1_PT_0 : STD_LOGIC; 
  signal irda_module_count4bit_0_MC_D1 : STD_LOGIC; 
  signal irda_module_count4bit_0_MC_D2 : STD_LOGIC; 
  signal irda_module_count4bit_2_MC_Q : STD_LOGIC; 
  signal irda_module_count4bit_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal irda_module_count4bit_2_MC_D : STD_LOGIC; 
  signal irda_module_count4bit_2_MC_D1_PT_0 : STD_LOGIC; 
  signal irda_module_count4bit_2_MC_D1 : STD_LOGIC; 
  signal irda_module_count4bit_2_MC_D2 : STD_LOGIC; 
  signal irda_module_count4bit_2_MC_D_TFF : STD_LOGIC; 
  signal irda_module_count4bit_1_MC_Q : STD_LOGIC; 
  signal irda_module_count4bit_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal irda_module_count4bit_1_MC_D : STD_LOGIC; 
  signal irda_module_count4bit_1_MC_D1 : STD_LOGIC; 
  signal irda_module_count4bit_1_MC_D2_PT_0 : STD_LOGIC; 
  signal irda_module_count4bit_1_MC_D2 : STD_LOGIC; 
  signal irda_module_count4bit_1_MC_D_TFF : STD_LOGIC; 
  signal irda_module_count4bit_3_MC_Q : STD_LOGIC; 
  signal irda_module_count4bit_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal irda_module_count4bit_3_MC_D : STD_LOGIC; 
  signal irda_module_count4bit_3_MC_D1_PT_0 : STD_LOGIC; 
  signal irda_module_count4bit_3_MC_D1 : STD_LOGIC; 
  signal irda_module_count4bit_3_MC_D2 : STD_LOGIC; 
  signal irda_module_count4bit_3_MC_D_TFF : STD_LOGIC; 
  signal overrun_MC_Q : STD_LOGIC; 
  signal overrun_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal overrun_MC_R_OR_PRLD : STD_LOGIC; 
  signal overrun_MC_D : STD_LOGIC; 
  signal overrun_MC_D1 : STD_LOGIC; 
  signal overrun_MC_UIM : STD_LOGIC; 
  signal overrun_MC_D2_PT_0 : STD_LOGIC; 
  signal overrun_MC_D2_PT_1 : STD_LOGIC; 
  signal overrun_MC_D2 : STD_LOGIC; 
  signal overrun_MC_D_TFF : STD_LOGIC; 
  signal parity_error_MC_Q : STD_LOGIC; 
  signal parity_error_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal parity_error_MC_R_OR_PRLD : STD_LOGIC; 
  signal parity_error_MC_D : STD_LOGIC; 
  signal parity_error_MC_D1 : STD_LOGIC; 
  signal parity_error_MC_UIM : STD_LOGIC; 
  signal parity_error_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_rx_paritygen : STD_LOGIC; 
  signal parity_error_MC_D2_PT_1 : STD_LOGIC; 
  signal parity_error_MC_D2_PT_2 : STD_LOGIC; 
  signal parity_error_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_paritygen_MC_Q : STD_LOGIC; 
  signal uart_module_rx_paritygen_MC_D : STD_LOGIC; 
  signal uart_module_rx_paritygen_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_paritygen_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_rx_paritygen_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_rx_paritygen_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_paritygen_MC_D_TFF : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR5_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR2_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR2_ctinst_4_OUT : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_459_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_2_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_N254_MC_D2_PT_3_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_tx_txdone1_MC_D1_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR1_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR1_ctinst_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR1_ctinst_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_clear_ff_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_clear_ff_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_clear_ff_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_clear_ff_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_clear_ff_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_clear_ff_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q0_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q0_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR3_ctinst_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR3_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR3_ctinst_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR3_ctinst_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR3_ctinst_4_OUT : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_count8reset_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_count8reset_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_count8reset_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_count8reset_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q3_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q3_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q1_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q1_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q1_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q2_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q2_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q2_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_irda_module_q2_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_idle_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_idle_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_0_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_0_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_0_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_1_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_1_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_1_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_2_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_2_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_2_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_3_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_3_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_3_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_4_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_4_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_4_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_5_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_5_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_5_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_6_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_6_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_6_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_7_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_7_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rsr_7_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxparity_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxparity_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxparity_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxstop_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxstop_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rx1_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_3_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_3_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_hunt_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_0_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_0_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_0_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_1_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uart_module_rx_rxcnt_1_MC_D2_PT_0_IN1 : STD_LOGIC;