irda_uart_timesim.vhd

adc转换功能的vhdl源码

  signal uart_module_rx_rxclk_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_3_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rxcnt_3_MC_D : STD_LOGIC; 
  signal uart_module_rx_rxcnt_3_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_3_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_hunt : STD_LOGIC; 
  signal uart_module_rx_rxcnt_3_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_3_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_3_MC_D2_PT_2 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_3_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_hunt_MC_Q : STD_LOGIC; 
  signal uart_module_rx_hunt_MC_D : STD_LOGIC; 
  signal uart_module_rx_hunt_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_hunt_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_hunt_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_0_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rxcnt_0_MC_D : STD_LOGIC; 
  signal uart_module_rx_rxcnt_0_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_0_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_0_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_0_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_1_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rxcnt_1_MC_D : STD_LOGIC; 
  signal uart_module_rx_rxcnt_1_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_1_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_1_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_1_MC_D2_PT_2 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_1_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_1_MC_D_TFF : STD_LOGIC; 
  signal uart_module_rx_rxcnt_2_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rxcnt_2_MC_D : STD_LOGIC; 
  signal uart_module_rx_rxcnt_2_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_2_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_2_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_2_MC_D2_PT_2 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_2_MC_D2_PT_3 : STD_LOGIC; 
  signal uart_module_rx_rxcnt_2_MC_D2 : STD_LOGIC; 
  signal irda_module_trigctl_MC_D1_PT_0 : STD_LOGIC; 
  signal irda_module_trigctl_MC_D1 : STD_LOGIC; 
  signal irda_module_trigctl_MC_D2 : STD_LOGIC; 
  signal irda_module_trigctl_MC_D_TFF : STD_LOGIC; 
  signal rxrdy_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal rxrdy_MC_Q : STD_LOGIC; 
  signal rxrdy_MC_R_OR_PRLD : STD_LOGIC; 
  signal rxrdy_MC_D : STD_LOGIC; 
  signal FOOBAR4_ctinst_4 : STD_LOGIC; 
  signal N73 : STD_LOGIC; 
  signal FOOBAR4_ctinst_0 : STD_LOGIC; 
  signal N_PZ_255 : STD_LOGIC; 
  signal N73_MC_Q : STD_LOGIC; 
  signal N73_MC_D : STD_LOGIC; 
  signal N73_MC_D1_PT_0 : STD_LOGIC; 
  signal N73_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_txparity : STD_LOGIC; 
  signal N73_MC_D2_PT_0 : STD_LOGIC; 
  signal N73_MC_D2_PT_1 : STD_LOGIC; 
  signal txrdy_MC_UIM : STD_LOGIC; 
  signal N73_MC_D2_PT_2 : STD_LOGIC; 
  signal N73_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_tsr_1_MC_Q : STD_LOGIC; 
  signal uart_module_tx_tsr_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_tsr_1_MC_D : STD_LOGIC; 
  signal uart_module_tx_tsr_1_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_tsr_1_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_tx_tsr_1_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_tx_tsr_1_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_tsr_2_MC_Q : STD_LOGIC; 
  signal uart_module_tx_tsr_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_tsr_2_MC_D : STD_LOGIC; 
  signal uart_module_tx_tsr_2_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_tsr_2_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_tx_tsr_2_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_tx_tsr_2_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_tsr_3_MC_Q : STD_LOGIC; 
  signal uart_module_tx_tsr_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_tsr_3_MC_D : STD_LOGIC; 
  signal uart_module_tx_tsr_3_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_tsr_3_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_tx_tsr_3_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_tx_tsr_3_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_tsr_4_MC_Q : STD_LOGIC; 
  signal uart_module_tx_tsr_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_tsr_4_MC_D : STD_LOGIC; 
  signal uart_module_tx_tsr_4_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_tsr_4_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_tx_tsr_4_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_tx_tsr_4_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_tsr_5_MC_Q : STD_LOGIC; 
  signal uart_module_tx_tsr_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_tsr_5_MC_D : STD_LOGIC; 
  signal uart_module_tx_tsr_5_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_tsr_5_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_tx_tsr_5_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_tx_tsr_5_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_tsr_6_MC_Q : STD_LOGIC; 
  signal uart_module_tx_tsr_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_tsr_6_MC_D : STD_LOGIC; 
  signal uart_module_tx_tsr_6_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_tsr_6_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_tx_tsr_6_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_tx_tsr_6_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_tsr_7_MC_Q : STD_LOGIC; 
  signal uart_module_tx_tsr_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_tsr_7_MC_D : STD_LOGIC; 
  signal uart_module_tx_tsr_7_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_tsr_7_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_tx_tsr_7_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_tx_tsr_7_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_tag1_MC_Q : STD_LOGIC; 
  signal uart_module_tx_tag1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_tag1_MC_D : STD_LOGIC; 
  signal uart_module_tx_tag1_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_tag1_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_tx_tag1_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_tx_tag1_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_tag2_MC_Q : STD_LOGIC; 
  signal uart_module_tx_tag2_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_tag2_MC_D : STD_LOGIC; 
  signal uart_module_tx_tag2_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_tag2_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_tag2_MC_D2 : STD_LOGIC; 
  signal txrdy_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal txrdy_MC_Q : STD_LOGIC; 
  signal txrdy_MC_S_OR_PRLD : STD_LOGIC; 
  signal txrdy_MC_D : STD_LOGIC; 
  signal txrdy_MC_D1_PT_0 : STD_LOGIC; 
  signal txrdy_MC_D1 : STD_LOGIC; 
  signal txrdy_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_write2_MC_Q : STD_LOGIC; 
  signal uart_module_tx_write2_MC_D : STD_LOGIC; 
  signal uart_module_tx_write2_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_write2_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_write2_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_thr_7_MC_Q : STD_LOGIC; 
  signal uart_module_tx_thr_7_MC_D : STD_LOGIC; 
  signal write_II_FCLK_tsimcreated_inv_Q : STD_LOGIC; 
  signal data_7_II_UIM : STD_LOGIC; 
  signal uart_module_tx_thr_7_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_thr_7_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_thr_7_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_thr_6_MC_Q : STD_LOGIC; 
  signal uart_module_tx_thr_6_MC_D : STD_LOGIC; 
  signal data_6_II_UIM : STD_LOGIC; 
  signal uart_module_tx_thr_6_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_thr_6_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_thr_6_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_thr_5_MC_Q : STD_LOGIC; 
  signal uart_module_tx_thr_5_MC_D : STD_LOGIC; 
  signal data_5_II_UIM : STD_LOGIC; 
  signal uart_module_tx_thr_5_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_thr_5_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_thr_5_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_thr_4_MC_Q : STD_LOGIC; 
  signal uart_module_tx_thr_4_MC_D : STD_LOGIC; 
  signal data_4_II_UIM : STD_LOGIC; 
  signal uart_module_tx_thr_4_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_thr_4_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_thr_4_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_thr_3_MC_Q : STD_LOGIC; 
  signal uart_module_tx_thr_3_MC_D : STD_LOGIC; 
  signal data_3_II_UIM : STD_LOGIC; 
  signal uart_module_tx_thr_3_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_thr_3_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_thr_3_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_thr_2_MC_Q : STD_LOGIC; 
  signal uart_module_tx_thr_2_MC_D : STD_LOGIC; 
  signal data_2_II_UIM : STD_LOGIC; 
  signal uart_module_tx_thr_2_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_thr_2_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_thr_2_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_thr_1_MC_Q : STD_LOGIC; 
  signal uart_module_tx_thr_1_MC_D : STD_LOGIC; 
  signal data_1_II_UIM : STD_LOGIC; 
  signal uart_module_tx_thr_1_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_thr_1_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_thr_1_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_txparity_MC_Q : STD_LOGIC; 
  signal uart_module_tx_txparity_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_txparity_MC_D : STD_LOGIC; 
  signal uart_module_tx_txparity_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_txparity_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_tx_txparity_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_tx_txparity_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_txparity_MC_D_TFF : STD_LOGIC; 
  signal N_PZ_255_MC_Q : STD_LOGIC; 
  signal N_PZ_255_MC_D : STD_LOGIC; 
  signal N_PZ_255_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_read1 : STD_LOGIC; 
  signal uart_module_rx_read2 : STD_LOGIC; 
  signal N_PZ_255_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_255_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_255_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_read1_MC_Q : STD_LOGIC; 
  signal uart_module_rx_read1_MC_D : STD_LOGIC; 
  signal uart_module_rx_read1_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_read1_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_read1_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_read2_MC_Q : STD_LOGIC; 
  signal uart_module_rx_read2_MC_D : STD_LOGIC; 
  signal uart_module_rx_read2_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_read2_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_read2_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_idle1_MC_Q : STD_LOGIC; 
  signal uart_module_rx_idle1_MC_D : STD_LOGIC; 
  signal uart_module_rx_idle1_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_idle1_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_idle1_MC_D2 : STD_LOGIC; 
  signal rxrdy_MC_D1_PT_0 : STD_LOGIC; 
  signal rxrdy_MC_D1 : STD_LOGIC; 
  signal rxrdy_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_txclk_MC_Q : STD_LOGIC; 
  signal uart_module_tx_txclk_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_txclk_MC_D : STD_LOGIC; 
  signal uart_module_tx_txclk_MC_CE : STD_LOGIC; 
  signal uart_module_tx_txclk_MC_CE_PT_0 : STD_LOGIC; 
  signal uart_module_tx_txclk_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_txclk_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_txclk_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_cnt_0_MC_Q : STD_LOGIC; 
  signal uart_module_tx_cnt_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_cnt_0_MC_D : STD_LOGIC; 
  signal uart_module_tx_cnt_0_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_cnt_0_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_cnt_0_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_cnt_2_MC_Q : STD_LOGIC; 
  signal uart_module_tx_cnt_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_cnt_2_MC_D : STD_LOGIC; 
  signal uart_module_tx_cnt_2_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_cnt_2_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_cnt_2_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_cnt_2_MC_D_TFF : STD_LOGIC; 
  signal uart_module_tx_cnt_1_MC_Q : STD_LOGIC; 
  signal uart_module_tx_cnt_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_cnt_1_MC_D : STD_LOGIC; 
  signal uart_module_tx_cnt_1_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_cnt_1_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_tx_cnt_1_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_cnt_1_MC_D_TFF : STD_LOGIC; 
  signal uart_module_tx_tsr_0_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_tsr_0_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_tx_tsr_0_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_tx_tsr_0_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_thr_0_MC_Q : STD_LOGIC; 
  signal uart_module_tx_thr_0_MC_D : STD_LOGIC; 
  signal data_0_II_UIM : STD_LOGIC; 
  signal uart_module_tx_thr_0_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_thr_0_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_thr_0_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rhr_0_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_0_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rhr_0_MC_D2 : STD_LOGIC; 
  signal data_1_MC_Q : STD_LOGIC; 
  signal data_1_MC_OE : STD_LOGIC; 
  signal data_1_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_1_MC_D : STD_LOGIC; 
  signal data_1_MC_D1_PT_0 : STD_LOGIC; 
  signal data_1_MC_D1 : STD_LOGIC; 
  signal data_1_MC_D2 : STD_LOGIC; 
  signal data_1_MC_BUFOE_OUT : STD_LOGIC; 
  signal uart_module_rx_rhr_1_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rhr_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_rx_rhr_1_MC_D : STD_LOGIC; 
  signal uart_module_rx_rhr_1_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_1_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rhr_1_MC_D2 : STD_LOGIC; 
  signal data_2_MC_Q : STD_LOGIC; 
  signal data_2_MC_OE : STD_LOGIC; 
  signal data_2_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_2_MC_D : STD_LOGIC; 
  signal data_2_MC_D1_PT_0 : STD_LOGIC; 
  signal data_2_MC_D1 : STD_LOGIC; 
  signal data_2_MC_D2 : STD_LOGIC; 
  signal data_2_MC_BUFOE_OUT : STD_LOGIC; 
  signal uart_module_rx_rhr_2_MC_Q : STD_LOGIC;