irda_uart_timesim.vhd

adc转换功能的vhdl源码

-- Xilinx Vhdl produced by program ngd2vhdl E.35
-- Command: -rpw 100 -tpw 1 -ar Structure -xon true -w irda_uart.nga irda_uart_timesim.vhd 
-- Input file: irda_uart.nga
-- Output file: irda_uart_timesim.vhd
-- Design name: irda_uart
-- Xilinx: C:/Xilinx_WebPACK_42
-- # of Entities: 1
-- Device: XCR3128XL-6-TQ144

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity irda_uart is
  port (
    reset : in STD_LOGIC := 'X'; 
    irrxd : in STD_LOGIC := 'X'; 
    mclkx16 : in STD_LOGIC := 'X'; 
    read : in STD_LOGIC := 'X'; 
    framing_error : out STD_LOGIC; 
    write : in STD_LOGIC := 'X'; 
    irtxd : out STD_LOGIC; 
    overrun : out STD_LOGIC; 
    parity_error : out STD_LOGIC; 
    rxrdy : out STD_LOGIC; 
    txrdy : out STD_LOGIC; 
    xPUP_0 : in STD_LOGIC := 'X'; 
    data : inout STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end irda_uart;

architecture Structure of irda_uart is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal data_0_MC_Q : STD_LOGIC; 
  signal data_0_MC_OE : STD_LOGIC; 
  signal data_0_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_0_MC_D : STD_LOGIC; 
  signal read_II_FCLK : STD_LOGIC; 
  signal read_II_FCLK_tsimcreated_inv_Q : STD_LOGIC; 
  signal data_0_MC_D1_PT_0 : STD_LOGIC; 
  signal data_0_MC_D1 : STD_LOGIC; 
  signal data_0_MC_D2 : STD_LOGIC; 
  signal data_0_MC_BUFOE_OUT : STD_LOGIC; 
  signal read_II_UIM : STD_LOGIC; 
  signal FOOBAR5_ctinst_0 : STD_LOGIC; 
  signal uart_module_rx_rhr_0_MC_Q : STD_LOGIC; 
  signal FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal uart_module_rx_rhr_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_rx_rhr_0_MC_D : STD_LOGIC; 
  signal mclkx16_II_FCLK : STD_LOGIC; 
  signal FOOBAR1_ctinst_4 : STD_LOGIC; 
  signal N_PZ_459 : STD_LOGIC; 
  signal FOOBAR2_ctinst_0 : STD_LOGIC; 
  signal uart_module_tx_N254 : STD_LOGIC; 
  signal FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal uart_module_rx_rxclk : STD_LOGIC; 
  signal FOOBAR2_ctinst_5 : STD_LOGIC; 
  signal reset_II_UIM : STD_LOGIC; 
  signal N_PZ_459_MC_Q : STD_LOGIC; 
  signal N_PZ_459_MC_D : STD_LOGIC; 
  signal N_PZ_459_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_459_MC_D1 : STD_LOGIC; 
  signal N_PZ_459_MC_D2 : STD_LOGIC; 
  signal xPUP_0_II_UIM : STD_LOGIC; 
  signal uart_module_tx_N254_MC_Q : STD_LOGIC; 
  signal uart_module_tx_N254_MC_D : STD_LOGIC; 
  signal uart_module_tx_N254_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_write1 : STD_LOGIC; 
  signal uart_module_tx_txdone1 : STD_LOGIC; 
  signal uart_module_tx_N254_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_tx_write2 : STD_LOGIC; 
  signal uart_module_tx_N254_MC_D2_PT_1 : STD_LOGIC; 
  signal uart_module_tx_tag1 : STD_LOGIC; 
  signal uart_module_tx_tag2 : STD_LOGIC; 
  signal uart_module_tx_N254_MC_D2_PT_2 : STD_LOGIC; 
  signal uart_module_tx_N254_MC_D2_PT_3 : STD_LOGIC; 
  signal uart_module_tx_N254_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_write1_MC_Q : STD_LOGIC; 
  signal uart_module_tx_write1_MC_D : STD_LOGIC; 
  signal write_II_UIM : STD_LOGIC; 
  signal uart_module_tx_write1_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_write1_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_write1_MC_D2 : STD_LOGIC; 
  signal write_II_FCLK : STD_LOGIC; 
  signal uart_module_tx_txdone1_MC_Q : STD_LOGIC; 
  signal uart_module_tx_txdone1_MC_D : STD_LOGIC; 
  signal uart_module_tx_txdone1_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_tx_txdone1_MC_D1 : STD_LOGIC; 
  signal uart_module_tx_txdone1_MC_D2 : STD_LOGIC; 
  signal uart_module_tx_tsr_0_MC_Q : STD_LOGIC; 
  signal uart_module_tx_tsr_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_tx_tsr_0_MC_D : STD_LOGIC; 
  signal FOOBAR1_ctinst_7 : STD_LOGIC; 
  signal irda_module_clear_ff : STD_LOGIC; 
  signal FOOBAR1_ctinst_0 : STD_LOGIC; 
  signal uart_module_rx_idle : STD_LOGIC; 
  signal rxrdy_MC_UIM : STD_LOGIC; 
  signal uart_module_rx_idle1 : STD_LOGIC; 
  signal FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal uart_module_tx_txclk : STD_LOGIC; 
  signal irda_module_clear_ff_MC_Q : STD_LOGIC; 
  signal irda_module_clear_ff_MC_R_OR_PRLD : STD_LOGIC; 
  signal irda_module_clear_ff_MC_D : STD_LOGIC; 
  signal irda_module_q0 : STD_LOGIC; 
  signal irda_module_q3 : STD_LOGIC; 
  signal irda_module_q1 : STD_LOGIC; 
  signal irda_module_trigctl : STD_LOGIC; 
  signal irda_module_q2 : STD_LOGIC; 
  signal irda_module_clear_ff_MC_D1_PT_0 : STD_LOGIC; 
  signal irda_module_clear_ff_MC_D1 : STD_LOGIC; 
  signal irda_module_clear_ff_MC_D2 : STD_LOGIC; 
  signal irda_module_q0_MC_Q : STD_LOGIC; 
  signal irda_module_q0_MC_R_OR_PRLD : STD_LOGIC; 
  signal irda_module_q0_MC_D : STD_LOGIC; 
  signal mclkx16_II_FCLK_tsimcreated_inv_Q : STD_LOGIC; 
  signal irda_module_q0_MC_D1 : STD_LOGIC; 
  signal irda_module_q0_MC_D2_PT_0 : STD_LOGIC; 
  signal irda_module_one_more : STD_LOGIC; 
  signal irda_module_q0_MC_D2_PT_1 : STD_LOGIC; 
  signal irda_module_q0_MC_D2 : STD_LOGIC; 
  signal irda_module_trigctl_MC_Q : STD_LOGIC; 
  signal FOOBAR3_ctinst_0 : STD_LOGIC; 
  signal irda_module_trigctl_MC_R_OR_PRLD : STD_LOGIC; 
  signal irda_module_trigctl_MC_D : STD_LOGIC; 
  signal irrxd_II_FCLK : STD_LOGIC; 
  signal irrxd_II_FCLK_tsimcreated_inv_Q : STD_LOGIC; 
  signal irda_module_count8reset : STD_LOGIC; 
  signal uart_module_rx_rx1 : STD_LOGIC; 
  signal FOOBAR3_ctinst_4 : STD_LOGIC; 
  signal FOOBAR3_ctinst_5 : STD_LOGIC; 
  signal irda_module_count8reset_MC_Q : STD_LOGIC; 
  signal irda_module_count8reset_MC_R_OR_PRLD : STD_LOGIC; 
  signal irda_module_count8reset_MC_D : STD_LOGIC; 
  signal irda_module_count8reset_MC_D1_PT_0 : STD_LOGIC; 
  signal irda_module_count8reset_MC_D1 : STD_LOGIC; 
  signal irda_module_count8reset_MC_D2 : STD_LOGIC; 
  signal irda_module_q3_MC_Q : STD_LOGIC; 
  signal irda_module_q3_MC_R_OR_PRLD : STD_LOGIC; 
  signal irda_module_q3_MC_D : STD_LOGIC; 
  signal irda_module_q3_MC_D1_PT_0 : STD_LOGIC; 
  signal irda_module_q3_MC_D1 : STD_LOGIC; 
  signal irda_module_q3_MC_D2_PT_0 : STD_LOGIC; 
  signal irda_module_q3_MC_D2_PT_1 : STD_LOGIC; 
  signal irda_module_q3_MC_D2_PT_2 : STD_LOGIC; 
  signal irda_module_q3_MC_D2 : STD_LOGIC; 
  signal irda_module_one_more_MC_Q : STD_LOGIC; 
  signal irda_module_one_more_MC_R_OR_PRLD : STD_LOGIC; 
  signal irda_module_one_more_MC_D : STD_LOGIC; 
  signal irda_module_one_more_MC_D1 : STD_LOGIC; 
  signal irda_module_one_more_MC_D2_PT_0 : STD_LOGIC; 
  signal irda_module_one_more_MC_D2 : STD_LOGIC; 
  signal irda_module_q1_MC_Q : STD_LOGIC; 
  signal irda_module_q1_MC_R_OR_PRLD : STD_LOGIC; 
  signal irda_module_q1_MC_D : STD_LOGIC; 
  signal irda_module_q1_MC_D1 : STD_LOGIC; 
  signal irda_module_q1_MC_D2_PT_0 : STD_LOGIC; 
  signal irda_module_q1_MC_D2_PT_1 : STD_LOGIC; 
  signal irda_module_q1_MC_D2_PT_2 : STD_LOGIC; 
  signal irda_module_q1_MC_D2 : STD_LOGIC; 
  signal irda_module_q1_MC_D_TFF : STD_LOGIC; 
  signal irda_module_q2_MC_Q : STD_LOGIC; 
  signal irda_module_q2_MC_R_OR_PRLD : STD_LOGIC; 
  signal irda_module_q2_MC_D : STD_LOGIC; 
  signal irda_module_q2_MC_D1 : STD_LOGIC; 
  signal irda_module_q2_MC_D2_PT_0 : STD_LOGIC; 
  signal irda_module_q2_MC_D2_PT_1 : STD_LOGIC; 
  signal irda_module_q2_MC_D2_PT_2 : STD_LOGIC; 
  signal irda_module_q2_MC_D2_PT_3 : STD_LOGIC; 
  signal irda_module_q2_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_idle_MC_Q : STD_LOGIC; 
  signal uart_module_rx_idle_MC_D : STD_LOGIC; 
  signal uart_module_rx_idle_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_idle_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_idle_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rsr_0_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rsr_0_MC_D : STD_LOGIC; 
  signal uart_module_rx_rsr_0_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rsr_0_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rsr_0_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rsr_1_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rsr_1_MC_D : STD_LOGIC; 
  signal uart_module_rx_rsr_1_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rsr_1_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rsr_1_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rsr_2_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rsr_2_MC_D : STD_LOGIC; 
  signal uart_module_rx_rsr_2_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rsr_2_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rsr_2_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rsr_3_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rsr_3_MC_D : STD_LOGIC; 
  signal uart_module_rx_rsr_3_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rsr_3_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rsr_3_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rsr_4_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rsr_4_MC_D : STD_LOGIC; 
  signal uart_module_rx_rsr_4_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rsr_4_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rsr_4_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rsr_5_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rsr_5_MC_D : STD_LOGIC; 
  signal uart_module_rx_rsr_5_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rsr_5_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rsr_5_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rsr_6_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rsr_6_MC_D : STD_LOGIC; 
  signal uart_module_rx_rsr_6_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rsr_6_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rsr_6_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rsr_7_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rsr_7_MC_D : STD_LOGIC; 
  signal uart_module_rx_rxparity : STD_LOGIC; 
  signal uart_module_rx_rsr_7_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rsr_7_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rsr_7_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rxparity_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rxparity_MC_D : STD_LOGIC; 
  signal uart_module_rx_rxstop : STD_LOGIC; 
  signal uart_module_rx_rxparity_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rxparity_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rxparity_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rxstop_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rxstop_MC_R_OR_PRLD : STD_LOGIC; 
  signal uart_module_rx_rxstop_MC_D : STD_LOGIC; 
  signal uart_module_rx_rxstop_MC_D1_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rxstop_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rxstop_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rx1_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rx1_MC_D : STD_LOGIC; 
  signal uart_module_rx_rx1_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rx1_MC_D2_PT_0 : STD_LOGIC; 
  signal uart_module_rx_rx1_MC_D2 : STD_LOGIC; 
  signal uart_module_rx_rxclk_MC_Q : STD_LOGIC; 
  signal uart_module_rx_rxclk_MC_D : STD_LOGIC; 
  signal uart_module_rx_rxclk_MC_D1 : STD_LOGIC; 
  signal uart_module_rx_rxclk_MC_D2_PT_0 : STD_LOGIC;