uart.vhd

adc转换功能的vhdl源码

-- *******************************************************************
-- 
-- Owner:	Xilinx Inc.
-- File:  	uart.vhd
--
-- Purpose: 	Top level UART description.  UART implements
-- 		a full duplex function.  This interface
-- 		interprets processor read/write parallel bus
-- 		protocol and translates to serial interface.
--
-- Created:	VHDL code generated by Visual HDL 8-15-01
--  
-- *******************************************************************


library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_MISC.all;
use ieee.STD_LOGIC_UNSIGNED.all;
 
use work.pkg_util.all;
 
entity uart is
  port (
        mclkx16 	: in STD_LOGIC;
        reset 		: in STD_LOGIC;
        read 		: in STD_LOGIC;
        write 		: in STD_LOGIC;
        data 		: inout STD_LOGIC_VECTOR (7 downto 0);
        sin 		: in STD_LOGIC;
        sout 		: out STD_LOGIC;
        rxrdy 		: out STD_LOGIC;
        txrdy 		: out STD_LOGIC;
        parity_error 	: out STD_LOGIC;
        framing_error 	: out STD_LOGIC;
        overrun 	: out STD_LOGIC
        );
end uart;
 

architecture behavior of uart is

component txmit
    port (
          mclkx16 	: in STD_LOGIC := 'Z';
          write 	: in STD_LOGIC := 'Z';
          reset 	: in STD_LOGIC := 'Z';
          sout 		: out STD_LOGIC;
          txrdy 	: out STD_LOGIC := 'Z';
          data 		: in STD_LOGIC_VECTOR (7 downto 0) := "ZZZZZZZZ"
          );
end component;

component rxcver
    port (
          mclkx16 	: in STD_LOGIC := 'Z';
          read 		: in STD_LOGIC := 'Z';
          sin 		: in STD_LOGIC := 'Z';
          reset 	: in STD_LOGIC := 'Z';
          rxrdy 	: out STD_LOGIC := 'Z';
          parity_error 	: out STD_LOGIC;
          framing_error : out STD_LOGIC;
          overrun 	: out STD_LOGIC;
          rxdata 	: out STD_LOGIC_VECTOR(7 downto 0 )
          );
end component;

signal rxdata : STD_LOGIC_VECTOR(7 downto 0 );  --  Intermediate output signals from receiver


begin
 
 
  -- Instantiation of the transmitter module
  tx: txmit
    port map (
              mclkx16,
              write,
              reset,
              sout,
              txrdy,
              data);
 
  --  Instantiation of the receiver module
  rx: rxcver
    port map (
              mclkx16,
              read,
              sin,
              reset,
              rxrdy,
              parity_error,
              framing_error,
              overrun,
              rxdata);
              
  --  Drives the data bus during data read, otherwise tri-state the data bus
  data <= rxdata when (read = '0' ) else "ZZZZZZZZ";
 
end ;