adder4.v

verilog 经典例子的源码 非常适用于初学verilog的朋友们

module adder4(cout,sum,ina,inb,cin);
output[3:0] sum;
output cout;
input[3:0] ina,inb;
input cin;
assign {cout,sum}=ina+inb+cin;
endmodule