ep.fit.summary

来自「DES加密算法的VHDL实现,采用流水线技术实现」· SUMMARY 代码 · 共 19 行

Fitter Status : Successful - Sat Aug 04 21:15:02 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : ep
Top-level Entity Name : ep
Family : Stratix III
Device : EP3SL50F484C2
Timing Models : Preliminary
Logic utilization : 0 %
    Combinational ALUTs : 0 / 38,000 ( 0 % )
    Memory ALUTs : 0 / 19,000 ( 0 % )
    Dedicated logic registers : 0 / 38,000 ( 0 % )
Total registers : 0
Total pins : 80 / 296 ( 27 % )
Total virtual pins : 0
Total block memory bits : 0 / 1,880,064 ( 0 % )
DSP block 18-bit elements : 0 / 216 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )