prev_cmp_test.qmsg

DES加密算法的VHDL实现,采用流水线技术实现

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "10 unused 2.50 6 4 0 " "Info: Number of I/O pins in group: 10 (unused VREF, 2.50 VCCIO, 6 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "Info: I/O standards used: 2.5 V." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use unused 0 24 " "Info: I/O bank number 1A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1C does not use unused 1 25 " "Info: I/O bank number 1C does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  25 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2C does not use unused 0 26 " "Info: I/O bank number 2C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2A does not use unused 0 24 " "Info: I/O bank number 2A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use unused 0 0 " "Info: I/O bank number 3A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3C does not use unused 0 24 " "Info: I/O bank number 3C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4C does not use unused 0 24 " "Info: I/O bank number 4C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4A does not use unused 0 0 " "Info: I/O bank number 4A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5A does not use unused 0 24 " "Info: I/O bank number 5A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5C does not use unused 0 26 " "Info: I/O bank number 5C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6C does not use unused 0 26 " "Info: I/O bank number 6C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6A does not use unused 0 24 " "Info: I/O bank number 6A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7A does not use unused 0 0 " "Info: I/O bank number 7A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7C does not use unused 0 24 " "Info: I/O bank number 7C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8C does not use unused 0 24 " "Info: I/O bank number 8C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use unused 0 0 " "Info: I/O bank number 8A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y13 X11_Y25 " "Info: The peak interconnect region extends from location X0_Y13 to location X11_Y25" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "EP3SL50F484C2 " "Warning: Timing characteristics of device EP3SL50F484C2 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0 "" 0}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_FIOMGR_MUST_USE_EXTERNAL_CLAMPING_DIODE_TOP_LEVEL" "4 " "Warning: Following 4 pins must use external clamping diodes." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rs\[46\] 2.5 V P16 " "Info: Pin rs\[46\] uses I/O standard 2.5 V at P16" {  } { { "test.vhd" "" { Text "E:/Muxplux/Vhdl/DES/test.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[46] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[46] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rs\[45\] 2.5 V M21 " "Info: Pin rs\[45\] uses I/O standard 2.5 V at M21" {  } { { "test.vhd" "" { Text "E:/Muxplux/Vhdl/DES/test.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[45] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[45] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rs\[44\] 2.5 V N22 " "Info: Pin rs\[44\] uses I/O standard 2.5 V at N22" {  } { { "test.vhd" "" { Text "E:/Muxplux/Vhdl/DES/test.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[44] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[44] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rs\[43\] 2.5 V N21 " "Info: Pin rs\[43\] uses I/O standard 2.5 V at N21" {  } { { "test.vhd" "" { Text "E:/Muxplux/Vhdl/DES/test.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[43] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[43] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins must use external clamping diodes." 0 0 "" 0}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_441_TOP_LEVEL" "6 " "Warning: Following 6 pins must meet Altera requirements for 3.3V, 3.0V, and 2.5V interfaces." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rs\[47\] 2.5 V D15 " "Info: Pin rs\[47\] uses I/O standard 2.5 V at D15" {  } { { "test.vhd" "" { Text "E:/Muxplux/Vhdl/DES/test.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[47] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[47] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rs\[42\] 2.5 V AA16 " "Info: Pin rs\[42\] uses I/O standard 2.5 V at AA16" {  } { { "test.vhd" "" { Text "E:/Muxplux/Vhdl/DES/test.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[42] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[42] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rs\[46\] 2.5 V P16 " "Info: Pin rs\[46\] uses I/O standard 2.5 V at P16" {  } { { "test.vhd" "" { Text "E:/Muxplux/Vhdl/DES/test.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[46] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[46] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rs\[45\] 2.5 V M21 " "Info: Pin rs\[45\] uses I/O standard 2.5 V at M21" {  } { { "test.vhd" "" { Text "E:/Muxplux/Vhdl/DES/test.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[45] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[45] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rs\[44\] 2.5 V N22 " "Info: Pin rs\[44\] uses I/O standard 2.5 V at N22" {  } { { "test.vhd" "" { Text "E:/Muxplux/Vhdl/DES/test.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[44] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[44] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rs\[43\] 2.5 V N21 " "Info: Pin rs\[43\] uses I/O standard 2.5 V at N21" {  } { { "test.vhd" "" { Text "E:/Muxplux/Vhdl/DES/test.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[43] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs[43] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins must meet Altera requirements for 3.3V, 3.0V, and 2.5V interfaces." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/Muxplux/Vhdl/DES/test.fit.smsg " "Info: Generated suppressed messages file E:/Muxplux/Vhdl/DES/test.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "325 " "Info: Allocated 325 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 05 19:12:35 2007 " "Info: Processing ended: Sun Aug 05 19:12:35 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Info: Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}