keyls.vhd

来自「DES加密算法的VHDL实现,采用流水线技术实现」· VHDL 代码 · 共 9 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity keyls is
port( c0x,d0x :	in 		std_logic_vector( 1 to 28 );
		k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x
		: 		out 	std_logic_vector( 1 to 48 )