test.map.rpt

DES加密算法的VHDL实现,采用流水线技术实现

; HDL message level                                                           ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                             ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                    ; 100                ; 100                ;
; Clock MUX Protection                                                        ; On                 ; On                 ;
; Use smart compilation                                                       ; Off                ; Off                ;
+-----------------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; test.vhd                         ; yes             ; User VHDL File  ; E:/Muxplux/Vhdl/DES/test.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------+


+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                  ;
+-----------------------------------------------+--------------+
; Resource                                      ; Usage        ;
+-----------------------------------------------+--------------+
; Estimated ALUTs Used                          ; 4            ;
;     -- Combinational ALUTs                    ; 4            ;
;     -- Memory ALUTs                           ; 0            ;
;     -- LUT_REGs                               ; 0            ;
; Dedicated logic registers                     ; 0            ;
;                                               ;              ;
; Estimated ALUTs Unavailable                   ; 0            ;
;     -- Due to unpartnered combinational logic ; 0            ;
;     -- Due to Memory ALUTs                    ; 0            ;
;     -- Due to LUT_REGs                        ; 0            ;
;                                               ;              ;
; Total combinational functions                 ; 4            ;
; Combinational ALUT usage by number of inputs  ;              ;
;     -- 7 input functions                      ; 0            ;
;     -- 6 input functions                      ; 0            ;
;     -- 5 input functions                      ; 0            ;
;     -- 4 input functions                      ; 4            ;
;     -- <=3 input functions                    ; 0            ;
;                                               ;              ;
; Combinational ALUTs by mode                   ;              ;
;     -- normal mode                            ; 4            ;
;     -- extended LUT mode                      ; 0            ;
;     -- arithmetic mode                        ; 0            ;
;     -- shared arithmetic mode                 ; 0            ;
;                                               ;              ;
; Estimated ALUT/register pairs used            ; 4            ;
;                                               ;              ;
; Total registers                               ; 0            ;
;     -- Dedicated logic registers              ; 0            ;
;     -- I/O registers                          ; 0            ;
;     -- LUT_REGs                               ; 0            ;
;                                               ;              ;
; Estimated ALMs:  partially or completely used ; 2            ;
;                                               ;              ;
; I/O pins                                      ; 10           ;
; Maximum fan-out node                          ; rs[44]~input ;
; Maximum fan-out                               ; 4            ;
; Total fan-out                                 ; 30           ;
; Average fan-out                               ; 1.25         ;
+-----------------------------------------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                       ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 12x12 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+-----------+------+--------------+---------------------+--------------+
; |test                      ; 4 (4)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 10   ; 0            ; |test               ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sun Aug 05 19:14:05 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test
Info: Found 2 design units, including 1 entities, in source file test.vhd
    Info: Found design unit 1: test-arch_test
    Info: Found entity 1: test
Info: Elaborating entity "test" for the top level hierarchy
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "rs[43]"
    Warning: No output dependent on input pin "rs[47]"
Info: Implemented 24 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 4 output pins
    Info: Implemented 4 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 149 megabytes of memory during processing
    Info: Processing ended: Sun Aug 05 19:14:08 2007
    Info: Elapsed time: 00:00:03