pc2.vhd

DES加密算法的VHDL实现,采用流水线技术实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pc2 is
port( c,d : in 	std_logic_vector( 1 to 28 );
		ct: out std_logic_vector( 1 to 48 )
	);
end entity pc2 ;
architecture arch_pc2 of pc2 is
signal cd : 	std_logic_vector( 1 to 56 );
begin 
	cd <= 	c & d ;
	ct <=  cd(14) & cd(17) & cd(11) & cd(24) & cd( 1) & cd( 5) &
           cd( 3) & cd(28) & cd(15) & cd( 6) & cd(21) & cd(10) &
           cd(23) & cd(19) & cd(12) & cd( 4) & cd(26) & cd( 8) &
           cd(16) & cd( 7) & cd(27) & cd(20) & cd(13) & cd( 2) &
           cd(41) & cd(52) & cd(31) & cd(37) & cd(47) & cd(55) &
           cd(30) & cd(40) & cd(51) & cd(45) & cd(33) & cd(48) &
           cd(44) & cd(49) & cd(39) & cd(56) & cd(34) & cd(53) &
           cd(46) & cd(42) & cd(50) & cd(36) & cd(29) & cd(32) ;
end architecture arch_pc2 ;