📄 pp.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pp is
port( pi : in std_logic_vector( 1 to 32 );
po : out std_logic_vector( 1 to 32 )
);
end entity pp ;
architecture arch_pp of pp is
begin
po <= pi(16) & pi( 7) & pi(20) & pi(21) & pi(29) & pi(12) & pi(28) & pi(17) &
pi( 1) & pi(15) & pi(23) & pi(26) & pi( 5) & pi(18) & pi(31) & pi(10) &
pi( 2) & pi( 8) & pi(24) & pi(14) & pi(32) & pi(27) & pi( 3) & pi( 9) &
pi(19) & pi(13) & pi(30) & pi( 6) & pi(22) & pi(11) & pi( 4) & pi(25) ;
end architecture arch_pp ;
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