prev_cmp_endes.map.qmsg

DES加密算法的VHDL实现,采用流水线技术实现

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "enLxorR ENLL:inst17\|enLxorR:b2v_inst4 " "Info: Elaborating entity \"enLxorR\" for hierarchy \"ENLL:inst17\|enLxorR:b2v_inst4\"" {  } { { "ENLL.vhd" "b2v_inst4" { Text "E:/Muxplux/Vhdl/DES/ENLL.vhd" 86 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "pp.vhd 2 1 " "Warning: Using design file pp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pp-arch_pp " "Info: Found design unit 1: pp-arch_pp" {  } { { "pp.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pp.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pp " "Info: Found entity 1: pp" {  } { { "pp.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pp.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pp ENLL:inst17\|pp:b2v_inst5 " "Info: Elaborating entity \"pp\" for hierarchy \"ENLL:inst17\|pp:b2v_inst5\"" {  } { { "ENLL.vhd" "b2v_inst5" { Text "E:/Muxplux/Vhdl/DES/ENLL.vhd" 91 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "sbox.vhd 2 1 " "Warning: Using design file sbox.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sbox-arch_sbox " "Info: Found design unit 1: sbox-arch_sbox" {  } { { "sbox.vhd" "" { Text "E:/Muxplux/Vhdl/DES/sbox.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sbox " "Info: Found entity 1: sbox" {  } { { "sbox.vhd" "" { Text "E:/Muxplux/Vhdl/DES/sbox.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sbox ENLL:inst17\|sbox:b2v_inst6 " "Info: Elaborating entity \"sbox\" for hierarchy \"ENLL:inst17\|sbox:b2v_inst6\"" {  } { { "ENLL.vhd" "b2v_inst6" { Text "E:/Muxplux/Vhdl/DES/ENLL.vhd" 95 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "keysch.vhd 6 3 " "Warning: Using design file keysch.vhd, which is not specified as a design file for the current project, but contains definitions for 6 design units and 3 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pc1-arch_pc1 " "Info: Found design unit 1: pc1-arch_pc1" {  } { { "keysch.vhd" "" { Text "E:/Muxplux/Vhdl/DES/keysch.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 pc2-arch_pc2 " "Info: Found design unit 2: pc2-arch_pc2" {  } { { "keysch.vhd" "" { Text "E:/Muxplux/Vhdl/DES/keysch.vhd" 35 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 keysch-arch_keysch " "Info: Found design unit 3: keysch-arch_keysch" {  } { { "keysch.vhd" "" { Text "E:/Muxplux/Vhdl/DES/keysch.vhd" 59 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pc1 " "Info: Found entity 1: pc1" {  } { { "keysch.vhd" "" { Text "E:/Muxplux/Vhdl/DES/keysch.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 pc2 " "Info: Found entity 2: pc2" {  } { { "keysch.vhd" "" { Text "E:/Muxplux/Vhdl/DES/keysch.vhd" 30 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 keysch " "Info: Found entity 3: keysch" {  } { { "keysch.vhd" "" { Text "E:/Muxplux/Vhdl/DES/keysch.vhd" 53 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "keysch keysch:inst2 " "Info: Elaborating entity \"keysch\" for hierarchy \"keysch:inst2\"" {  } { { "ENDES.bdf" "inst2" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { { 368 -32 128 688 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pc1 keysch:inst2\|pc1:pc_1 " "Info: Elaborating entity \"pc1\" for hierarchy \"keysch:inst2\|pc1:pc_1\"" {  } { { "keysch.vhd" "pc_1" { Text "E:/Muxplux/Vhdl/DES/keysch.vhd" 77 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pc2 keysch:inst2\|pc2:key1 " "Info: Elaborating entity \"pc2\" for hierarchy \"keysch:inst2\|pc2:key1\"" {  } { { "keysch.vhd" "key1" { Text "E:/Muxplux/Vhdl/DES/keysch.vhd" 127 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "ip.vhd 2 1 " "Warning: Using design file ip.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ip-arch_ip " "Info: Found design unit 1: ip-arch_ip" {  } { { "ip.vhd" "" { Text "E:/Muxplux/Vhdl/DES/ip.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ip " "Info: Found entity 1: ip" {  } { { "ip.vhd" "" { Text "E:/Muxplux/Vhdl/DES/ip.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ip ip:inst " "Info: Elaborating entity \"ip\" for hierarchy \"ip:inst\"" {  } { { "ENDES.bdf" "inst" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { { 56 120 264 152 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Warning: Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[8\] " "Warning: No output dependent on input pin \"key\[8\]\"" {  } { { "ENDES.bdf" "" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { { 392 -272 -104 408 "key\[1..64\]" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[16\] " "Warning: No output dependent on input pin \"key\[16\]\"" {  } { { "ENDES.bdf" "" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { { 392 -272 -104 408 "key\[1..64\]" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[24\] " "Warning: No output dependent on input pin \"key\[24\]\"" {  } { { "ENDES.bdf" "" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { { 392 -272 -104 408 "key\[1..64\]" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[32\] " "Warning: No output dependent on input pin \"key\[32\]\"" {  } { { "ENDES.bdf" "" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { { 392 -272 -104 408 "key\[1..64\]" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[40\] " "Warning: No output dependent on input pin \"key\[40\]\"" {  } { { "ENDES.bdf" "" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { { 392 -272 -104 408 "key\[1..64\]" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[48\] " "Warning: No output dependent on input pin \"key\[48\]\"" {  } { { "ENDES.bdf" "" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { { 392 -272 -104 408 "key\[1..64\]" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[56\] " "Warning: No output dependent on input pin \"key\[56\]\"" {  } { { "ENDES.bdf" "" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { { 392 -272 -104 408 "key\[1..64\]" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[64\] " "Warning: No output dependent on input pin \"key\[64\]\"" {  } { { "ENDES.bdf" "" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { { 392 -272 -104 408 "key\[1..64\]" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1986 " "Info: Implemented 1986 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "128 " "Info: Implemented 128 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "128 " "Info: Implemented 128 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "1474 " "Info: Implemented 1474 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "176 " "Info: Allocated 176 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 07 10:57:02 2007 " "Info: Processing ended: Tue Aug 07 10:57:02 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:01:24 " "Info: Elapsed time: 00:01:24" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}