prev_cmp_endes.map.qmsg

DES加密算法的VHDL实现,采用流水线技术实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 07 10:55:38 2007 " "Info: Processing started: Tue Aug 07 10:55:38 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ENDES -c ENDES " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ENDES -c ENDES" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "enLxorR.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file enLxorR.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 enLxorR-arch_enLxorR " "Info: Found design unit 1: enLxorR-arch_enLxorR" {  } { { "enLxorR.vhd" "" { Text "E:/Muxplux/Vhdl/DES/enLxorR.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 enLxorR " "Info: Found entity 1: enLxorR" {  } { { "enLxorR.vhd" "" { Text "E:/Muxplux/Vhdl/DES/enLxorR.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ENDES.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ENDES.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ENDES " "Info: Found entity 1: ENDES" {  } { { "ENDES.bdf" "" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ENDES " "Info: Elaborating entity \"ENDES\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "fp.vhd 2 1 " "Warning: Using design file fp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fp-arch_fp " "Info: Found design unit 1: fp-arch_fp" {  } { { "fp.vhd" "" { Text "E:/Muxplux/Vhdl/DES/fp.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fp " "Info: Found entity 1: fp" {  } { { "fp.vhd" "" { Text "E:/Muxplux/Vhdl/DES/fp.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp fp:inst18 " "Info: Elaborating entity \"fp\" for hierarchy \"fp:inst18\"" {  } { { "ENDES.bdf" "inst18" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { { 1736 712 840 1832 "inst18" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "ENLL.vhd 2 1 " "Warning: Using design file ENLL.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ENLL-bdf_type " "Info: Found design unit 1: ENLL-bdf_type" {  } { { "ENLL.vhd" "" { Text "E:/Muxplux/Vhdl/DES/ENLL.vhd" 33 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ENLL " "Info: Found entity 1: ENLL" {  } { { "ENLL.vhd" "" { Text "E:/Muxplux/Vhdl/DES/ENLL.vhd" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "ENLL " "Warning: Found the following files while searching for definition of entity \"ENLL\", but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "ENLL.bdf " "Warning: File: ENLL.bdf" {  } {  } 0 0 "File: %1!s!" 0 0 "" 0}  } {  } 0 0 "Found the following files while searching for definition of entity \"%1!s!\", but did not use these files because already using a different file containing the entity definition" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ENLL ENLL:inst17 " "Info: Elaborating entity \"ENLL\" for hierarchy \"ENLL:inst17\"" {  } { { "ENDES.bdf" "inst17" { Schematic "E:/Muxplux/Vhdl/DES/ENDES.bdf" { { 1752 448 592 1848 "inst17" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "ep.vhd 2 1 " "Warning: Using design file ep.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ep-arch_ep " "Info: Found design unit 1: ep-arch_ep" {  } { { "ep.vhd" "" { Text "E:/Muxplux/Vhdl/DES/ep.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ep " "Info: Found entity 1: ep" {  } { { "ep.vhd" "" { Text "E:/Muxplux/Vhdl/DES/ep.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ep ENLL:inst17\|ep:b2v_inst " "Info: Elaborating entity \"ep\" for hierarchy \"ENLL:inst17\|ep:b2v_inst\"" {  } { { "ENLL.vhd" "b2v_inst" { Text "E:/Muxplux/Vhdl/DES/ENLL.vhd" 77 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "ep_xor_key.vhd 2 1 " "Warning: Using design file ep_xor_key.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ep_xor_key-arch_ep_xor_key " "Info: Found design unit 1: ep_xor_key-arch_ep_xor_key" {  } { { "ep_xor_key.vhd" "" { Text "E:/Muxplux/Vhdl/DES/ep_xor_key.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ep_xor_key " "Info: Found entity 1: ep_xor_key" {  } { { "ep_xor_key.vhd" "" { Text "E:/Muxplux/Vhdl/DES/ep_xor_key.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ep_xor_key ENLL:inst17\|ep_xor_key:b2v_inst1 " "Info: Elaborating entity \"ep_xor_key\" for hierarchy \"ENLL:inst17\|ep_xor_key:b2v_inst1\"" {  } { { "ENLL.vhd" "b2v_inst1" { Text "E:/Muxplux/Vhdl/DES/ENLL.vhd" 81 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}