des_ip.map.qmsg

DES加密算法的VHDL实现,采用流水线技术实现

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pp RR:inst16\|pp:b2v_inst2 " "Info: Elaborating entity \"pp\" for hierarchy \"RR:inst16\|pp:b2v_inst2\"" {  } { { "RR.vhd" "b2v_inst2" { Text "E:/VhdlorVerilogExamples/DES/RR.vhd" 86 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lxorr.vhd 2 1 " "Warning: Using design file lxorr.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LxorR-arch_LxorR " "Info: Found design unit 1: LxorR-arch_LxorR" {  } { { "lxorr.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/lxorr.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 LxorR " "Info: Found entity 1: LxorR" {  } { { "lxorr.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/lxorr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lxorr RR:inst16\|lxorr:b2v_inst3 " "Info: Elaborating entity \"lxorr\" for hierarchy \"RR:inst16\|lxorr:b2v_inst3\"" {  } { { "RR.vhd" "b2v_inst3" { Text "E:/VhdlorVerilogExamples/DES/RR.vhd" 90 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sbox.vhd 2 1 " "Warning: Using design file sbox.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sbox-arch_sbox " "Info: Found design unit 1: sbox-arch_sbox" {  } { { "sbox.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/sbox.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sbox " "Info: Found entity 1: sbox" {  } { { "sbox.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/sbox.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sbox RR:inst16\|sbox:b2v_inst5 " "Info: Elaborating entity \"sbox\" for hierarchy \"RR:inst16\|sbox:b2v_inst5\"" {  } { { "RR.vhd" "b2v_inst5" { Text "E:/VhdlorVerilogExamples/DES/RR.vhd" 95 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "keysch.vhd 6 3 " "Warning: Using design file keysch.vhd, which is not specified as a design file for the current project, but contains definitions for 6 design units and 3 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pc1-arch_pc1 " "Info: Found design unit 1: pc1-arch_pc1" {  } { { "keysch.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 pc2-arch_pc2 " "Info: Found design unit 2: pc2-arch_pc2" {  } { { "keysch.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 35 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 keysch-arch_keysch " "Info: Found design unit 3: keysch-arch_keysch" {  } { { "keysch.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 59 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pc1 " "Info: Found entity 1: pc1" {  } { { "keysch.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 pc2 " "Info: Found entity 2: pc2" {  } { { "keysch.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 30 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 keysch " "Info: Found entity 3: keysch" {  } { { "keysch.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 53 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "keysch keysch:inst2 " "Info: Elaborating entity \"keysch\" for hierarchy \"keysch:inst2\"" {  } { { "DES_IP.bdf" "inst2" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 672 -32 128 992 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pc1 keysch:inst2\|pc1:pc_1 " "Info: Elaborating entity \"pc1\" for hierarchy \"keysch:inst2\|pc1:pc_1\"" {  } { { "keysch.vhd" "pc_1" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 77 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pc2 keysch:inst2\|pc2:key1 " "Info: Elaborating entity \"pc2\" for hierarchy \"keysch:inst2\|pc2:key1\"" {  } { { "keysch.vhd" "key1" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 127 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ip.vhd 2 1 " "Warning: Using design file ip.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ip-arch_ip " "Info: Found design unit 1: ip-arch_ip" {  } { { "ip.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/ip.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ip " "Info: Found entity 1: ip" {  } { { "ip.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/ip.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ip ip:inst19 " "Info: Elaborating entity \"ip\" for hierarchy \"ip:inst19\"" {  } { { "DES_IP.bdf" "inst19" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 48 -8 136 144 "inst19" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Warning: Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[8\] " "Warning (15610): No output dependent on input pin \"key\[8\]\"" {  } { { "DES_IP.bdf" "" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 696 -232 -64 712 "key\[1..64\]" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[16\] " "Warning (15610): No output dependent on input pin \"key\[16\]\"" {  } { { "DES_IP.bdf" "" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 696 -232 -64 712 "key\[1..64\]" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[24\] " "Warning (15610): No output dependent on input pin \"key\[24\]\"" {  } { { "DES_IP.bdf" "" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 696 -232 -64 712 "key\[1..64\]" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[32\] " "Warning (15610): No output dependent on input pin \"key\[32\]\"" {  } { { "DES_IP.bdf" "" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 696 -232 -64 712 "key\[1..64\]" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[40\] " "Warning (15610): No output dependent on input pin \"key\[40\]\"" {  } { { "DES_IP.bdf" "" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 696 -232 -64 712 "key\[1..64\]" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[48\] " "Warning (15610): No output dependent on input pin \"key\[48\]\"" {  } { { "DES_IP.bdf" "" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 696 -232 -64 712 "key\[1..64\]" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[56\] " "Warning (15610): No output dependent on input pin \"key\[56\]\"" {  } { { "DES_IP.bdf" "" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 696 -232 -64 712 "key\[1..64\]" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[64\] " "Warning (15610): No output dependent on input pin \"key\[64\]\"" {  } { { "DES_IP.bdf" "" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 696 -232 -64 712 "key\[1..64\]" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "4160 " "Info: Implemented 4160 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "128 " "Info: Implemented 128 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "64 " "Info: Implemented 64 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "3968 " "Info: Implemented 3968 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "180 " "Info: Peak virtual memory: 180 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 06 10:29:04 2009 " "Info: Processing ended: Wed May 06 10:29:04 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:04:57 " "Info: Elapsed time: 00:04:57" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:04:56 " "Info: Total CPU time (on all processors): 00:04:56" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}