des_ip.map.qmsg

DES加密算法的VHDL实现,采用流水线技术实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 06 10:24:07 2009 " "Info: Processing started: Wed May 06 10:24:07 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DES_IP -c DES_IP " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DES_IP -c DES_IP" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DES_IP.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DES_IP.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DES_IP " "Info: Found entity 1: DES_IP" {  } { { "DES_IP.bdf" "" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DES_IP " "Info: Elaborating entity \"DES_IP\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "fp.vhd 2 1 " "Warning: Using design file fp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fp-arch_fp " "Info: Found design unit 1: fp-arch_fp" {  } { { "fp.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/fp.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fp " "Info: Found entity 1: fp" {  } { { "fp.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/fp.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp fp:inst18 " "Info: Elaborating entity \"fp\" for hierarchy \"fp:inst18\"" {  } { { "DES_IP.bdf" "inst18" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 1712 656 784 1808 "inst18" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "RR.vhd 2 1 " "Warning: Using design file RR.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RR-bdf_type " "Info: Found design unit 1: RR-bdf_type" {  } { { "RR.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/RR.vhd" 33 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 RR " "Info: Found entity 1: RR" {  } { { "RR.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/RR.vhd" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "RR " "Warning (12300): Found the following files while searching for definition of entity \"RR\", but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "RR.bdf " "Warning: File: RR.bdf" {  } {  } 0 0 "File: %1!s!" 0 0 "" 0 0}  } {  } 0 12300 "Found the following files while searching for definition of entity \"%1!s!\", but did not use these files because already using a different file containing the entity definition" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RR RR:inst16 " "Info: Elaborating entity \"RR\" for hierarchy \"RR:inst16\"" {  } { { "DES_IP.bdf" "inst16" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 1616 384 528 1712 "inst16" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ep.vhd 2 1 " "Warning: Using design file ep.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ep-arch_ep " "Info: Found design unit 1: ep-arch_ep" {  } { { "ep.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/ep.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ep " "Info: Found entity 1: ep" {  } { { "ep.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/ep.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ep RR:inst16\|ep:b2v_inst " "Info: Elaborating entity \"ep\" for hierarchy \"RR:inst16\|ep:b2v_inst\"" {  } { { "RR.vhd" "b2v_inst" { Text "E:/VhdlorVerilogExamples/DES/RR.vhd" 77 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ep_xor_key.vhd 2 1 " "Warning: Using design file ep_xor_key.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ep_xor_key-arch_ep_xor_key " "Info: Found design unit 1: ep_xor_key-arch_ep_xor_key" {  } { { "ep_xor_key.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/ep_xor_key.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ep_xor_key " "Info: Found entity 1: ep_xor_key" {  } { { "ep_xor_key.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/ep_xor_key.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ep_xor_key RR:inst16\|ep_xor_key:b2v_inst1 " "Info: Elaborating entity \"ep_xor_key\" for hierarchy \"RR:inst16\|ep_xor_key:b2v_inst1\"" {  } { { "RR.vhd" "b2v_inst1" { Text "E:/VhdlorVerilogExamples/DES/RR.vhd" 81 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "pp.vhd 2 1 " "Warning: Using design file pp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pp-arch_pp " "Info: Found design unit 1: pp-arch_pp" {  } { { "pp.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/pp.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pp " "Info: Found entity 1: pp" {  } { { "pp.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/pp.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}