prev_cmp_des_ip.qmsg

DES加密算法的VHDL实现,采用流水线技术实现

{ "Warning" "WSGN_SEARCH_FILE" "lxorr.vhd 2 1 " "Warning: Using design file lxorr.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LxorR-arch_LxorR " "Info: Found design unit 1: LxorR-arch_LxorR" {  } { { "lxorr.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/lxorr.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 LxorR " "Info: Found entity 1: LxorR" {  } { { "lxorr.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/lxorr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lxorr RR:inst16\|lxorr:b2v_inst3 " "Info: Elaborating entity \"lxorr\" for hierarchy \"RR:inst16\|lxorr:b2v_inst3\"" {  } { { "RR.vhd" "b2v_inst3" { Text "E:/VhdlorVerilogExamples/DES/RR.vhd" 90 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sbox.vhd 2 1 " "Warning: Using design file sbox.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sbox-arch_sbox " "Info: Found design unit 1: sbox-arch_sbox" {  } { { "sbox.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/sbox.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sbox " "Info: Found entity 1: sbox" {  } { { "sbox.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/sbox.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sbox RR:inst16\|sbox:b2v_inst5 " "Info: Elaborating entity \"sbox\" for hierarchy \"RR:inst16\|sbox:b2v_inst5\"" {  } { { "RR.vhd" "b2v_inst5" { Text "E:/VhdlorVerilogExamples/DES/RR.vhd" 95 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "keysch.vhd 6 3 " "Warning: Using design file keysch.vhd, which is not specified as a design file for the current project, but contains definitions for 6 design units and 3 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pc1-arch_pc1 " "Info: Found design unit 1: pc1-arch_pc1" {  } { { "keysch.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 pc2-arch_pc2 " "Info: Found design unit 2: pc2-arch_pc2" {  } { { "keysch.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 35 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 keysch-arch_keysch " "Info: Found design unit 3: keysch-arch_keysch" {  } { { "keysch.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 59 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pc1 " "Info: Found entity 1: pc1" {  } { { "keysch.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 pc2 " "Info: Found entity 2: pc2" {  } { { "keysch.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 30 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 keysch " "Info: Found entity 3: keysch" {  } { { "keysch.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 53 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "keysch keysch:inst2 " "Info: Elaborating entity \"keysch\" for hierarchy \"keysch:inst2\"" {  } { { "DES_IP.bdf" "inst2" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 672 -32 128 992 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pc1 keysch:inst2\|pc1:pc_1 " "Info: Elaborating entity \"pc1\" for hierarchy \"keysch:inst2\|pc1:pc_1\"" {  } { { "keysch.vhd" "pc_1" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 77 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pc2 keysch:inst2\|pc2:key1 " "Info: Elaborating entity \"pc2\" for hierarchy \"keysch:inst2\|pc2:key1\"" {  } { { "keysch.vhd" "key1" { Text "E:/VhdlorVerilogExamples/DES/keysch.vhd" 127 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}