prev_cmp_des_ip.qmsg

DES加密算法的VHDL实现,采用流水线技术实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 06 10:15:31 2009 " "Info: Processing started: Wed May 06 10:15:31 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DES_IP -c DES_IP " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DES_IP -c DES_IP" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DES_IP.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DES_IP.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DES_IP " "Info: Found entity 1: DES_IP" {  } { { "DES_IP.bdf" "" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DES_IP " "Info: Elaborating entity \"DES_IP\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "fp.vhd 2 1 " "Warning: Using design file fp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fp-arch_fp " "Info: Found design unit 1: fp-arch_fp" {  } { { "fp.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/fp.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fp " "Info: Found entity 1: fp" {  } { { "fp.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/fp.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp fp:inst18 " "Info: Elaborating entity \"fp\" for hierarchy \"fp:inst18\"" {  } { { "DES_IP.bdf" "inst18" { Schematic "E:/VhdlorVerilogExamples/DES/DES_IP.bdf" { { 1712 656 784 1808 "inst18" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "RR.vhd 2 1 " "Warning: Using design file RR.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RR-bdf_type " "Info: Found design unit 1: RR-bdf_type" {  } { { "RR.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/RR.vhd" 33 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 RR " "Info: Found entity 1: RR" {  } { { "RR.vhd" "" { Text "E:/VhdlorVerilogExamples/DES/RR.vhd" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}