pc1.tan.qmsg

DES加密算法的VHDL实现,采用流水线技术实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 04 19:09:23 2007 " "Info: Processing started: Sat Aug 04 19:09:23 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off pc1 -c pc1 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pc1 -c pc1 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "key\[36\] c0x\[28\] 7.241 ns Longest " "Info: Longest tpd from source pin \"key\[36\]\" to destination pin \"c0x\[28\]\" is 7.241 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns key\[36\] 1 PIN PIN_R9 1 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_R9; Fanout = 1; PIN Node = 'key\[36\]'" {  } { { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { key[36] } "NODE_NAME" } } { "pc1.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pc1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.484 ns) + CELL(1.622 ns) 7.241 ns c0x\[28\] 2 PIN PIN_T9 0 " "Info: 2: + IC(4.484 ns) + CELL(1.622 ns) = 7.241 ns; Loc. = PIN_T9; Fanout = 0; PIN Node = 'c0x\[28\]'" {  } { { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.106 ns" { key[36] c0x[28] } "NODE_NAME" } } { "pc1.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pc1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.757 ns ( 38.07 % ) " "Info: Total cell delay = 2.757 ns ( 38.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.484 ns ( 61.93 % ) " "Info: Total interconnect delay = 4.484 ns ( 61.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "7.241 ns" { key[36] c0x[28] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera quartus ii 7.1/quartus/bin/Technology_Viewer.qrui" "7.241 ns" { key[36] key[36]~out0 c0x[28] } { 0.000ns 0.000ns 4.484ns } { 0.000ns 1.135ns 1.622ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 04 19:09:25 2007 " "Info: Processing ended: Sat Aug 04 19:09:25 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}