prev_cmp_pc1.map.qmsg

DES加密算法的VHDL实现,采用流水线技术实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 04 19:07:13 2007 " "Info: Processing started: Sat Aug 04 19:07:13 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pc1 -c pc1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pc1 -c pc1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pc1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pc1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pc1-arch_pc1 " "Info: Found design unit 1: pc1-arch_pc1" {  } { { "pc1.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pc1.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pc1 " "Info: Found entity 1: pc1" {  } { { "pc1.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pc1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pc1 " "Info: Elaborating entity \"pc1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Warning: Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[64\] " "Warning: No output dependent on input pin \"key\[64\]\"" {  } { { "pc1.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pc1.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[56\] " "Warning: No output dependent on input pin \"key\[56\]\"" {  } { { "pc1.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pc1.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[48\] " "Warning: No output dependent on input pin \"key\[48\]\"" {  } { { "pc1.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pc1.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[40\] " "Warning: No output dependent on input pin \"key\[40\]\"" {  } { { "pc1.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pc1.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[32\] " "Warning: No output dependent on input pin \"key\[32\]\"" {  } { { "pc1.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pc1.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[24\] " "Warning: No output dependent on input pin \"key\[24\]\"" {  } { { "pc1.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pc1.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[16\] " "Warning: No output dependent on input pin \"key\[16\]\"" {  } { { "pc1.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pc1.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "key\[8\] " "Warning: No output dependent on input pin \"key\[8\]\"" {  } { { "pc1.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pc1.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "120 " "Info: Implemented 120 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "64 " "Info: Implemented 64 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "56 " "Info: Implemented 56 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "148 " "Info: Allocated 148 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 04 19:07:15 2007 " "Info: Processing ended: Sat Aug 04 19:07:15 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}