test.fit.rpt

DES加密算法的VHDL实现,采用流水线技术实现

; LAB Constraint 'aclear used constraint' - Fit Attempt 1                    ; 0:2        ;
; LAB Constraint 'synch load or synch clear used constraint' - Fit Attempt 1 ; 0:2        ;
; LAB Constraint 'synch load or synch clear used constraint' - Fit Attempt 1 ; 0:2        ;
; LAB Constraint 'sync clear used constraint' - Fit Attempt 1                ; 0:2        ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                  ; 0:2        ;
; LEs in Chains - Fit Attempt 1                                              ; 0          ;
; LEs in Long Chains - Fit Attempt 1                                         ; 0          ;
; LABs with Chains - Fit Attempt 1                                           ; 0          ;
; LABs with Multiple Chains - Fit Attempt 1                                  ; 0          ;
; Time - Fit Attempt 1                                                       ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1                                        ; 0.016      ;
+----------------------------------------------------------------------------+------------+


+-------------------------------------------------+
; Advanced Data - Placement                       ;
+------------------------------------+------------+
; Name                               ; Value      ;
+------------------------------------+------------+
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 2 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Early Wire Use - Fit Attempt 1     ; 0          ;
; Early Slack - Fit Attempt 1        ; 2147483639 ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 3 - Fit Attempt 1   ; 0          ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff         ;
; Mid Wire Use - Fit Attempt 1       ; 0          ;
; Mid Slack - Fit Attempt 1          ; 2147483639 ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff         ;
; Late Wire Use - Fit Attempt 1      ; 0          ;
; Late Slack - Fit Attempt 1         ; 2147483639 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000      ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff         ;
; Time - Fit Attempt 1               ; 0          ;
+------------------------------------+------------+


+-------------------------------------------------+
; Advanced Data - Routing                         ;
+------------------------------------+------------+
; Name                               ; Value      ;
+------------------------------------+------------+
; Early Slack - Fit Attempt 1        ; 2147483639 ;
; Early Wire Use - Fit Attempt 1     ; 0          ;
; Peak Regional Wire - Fit Attempt 1 ; 0          ;
; Mid Slack - Fit Attempt 1          ; 2147483639 ;
; Late Slack - Fit Attempt 1         ; 2147483639 ;
; Late Wire Use - Fit Attempt 1      ; 0          ;
; Time - Fit Attempt 1               ; 1          ;
+------------------------------------+------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sun Aug 05 19:14:09 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off test -c test
Info: Automatically selected device EP3SL50F484C2 for design test
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Info: Compilation Report contains advanced information. Specifications for device EP3SL50F484C2 are subject to change. Contact Altera for information on availability. No programming file will be generated.
Info: Compilation Report contains advanced information. Specifications for device(s) in the current compile are subject to change. Contact Altera for information on availability. No pin-out will be generated.
    Info: Specifications for device EP3SL50F484C2 are subject to change. Contact Altera for information on availability.
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 24 of 24 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP3SL70F484C2 is compatible
    Info: Device EP3SE50F484C2 is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
    Info: Pin ~ALTERA_DATA0~ is reserved at location J18
Warning: No exact pin location assignment(s) for 10 pins of 10 total pins
    Info: Pin rs[43] not assigned to an exact location on the device
    Info: Pin rs[47] not assigned to an exact location on the device
    Info: Pin so[31] not assigned to an exact location on the device
    Info: Pin so[30] not assigned to an exact location on the device
    Info: Pin so[29] not assigned to an exact location on the device
    Info: Pin so[28] not assigned to an exact location on the device
    Info: Pin rs[44] not assigned to an exact location on the device
    Info: Pin rs[45] not assigned to an exact location on the device
    Info: Pin rs[46] not assigned to an exact location on the device
    Info: Pin rs[42] not assigned to an exact location on the device
Info: Fitter is using the TimeQuest Timing Analyzer
Critical Warning: SDC file not found: 'test.sdc'
Info: No base clocks found in the design. Calling "derive_clocks -period 1.0"
Warning: No clocks defined in design.
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 10 (unused VREF, 2.50 VCCIO, 6 input, 4 output, 0 bidirectional)
        Info: I/O standards used: 2.5 V.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
        Info: I/O bank number 1C does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  25 pins available
        Info: I/O bank number 2C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available
        Info: I/O bank number 2A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
        Info: I/O bank number 3A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 3C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
        Info: I/O bank number 4C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
        Info: I/O bank number 4A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 5A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
        Info: I/O bank number 5C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available
        Info: I/O bank number 6C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available
        Info: I/O bank number 6A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
        Info: I/O bank number 7A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 7C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
        Info: I/O bank number 8C does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
        Info: I/O bank number 8A does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y13 to location X11_Y25
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Timing characteristics of device EP3SL50F484C2 are preliminary
Info: Delay annotation completed successfully
Warning: Following 4 pins must use external clamping diodes.
    Info: Pin rs[44] uses I/O standard 2.5 V at P16
    Info: Pin rs[45] uses I/O standard 2.5 V at M21
    Info: Pin rs[46] uses I/O standard 2.5 V at N22
    Info: Pin rs[42] uses I/O standard 2.5 V at N21
Warning: Following 6 pins must meet Altera requirements for 3.3V, 3.0V, and 2.5V interfaces.
    Info: Pin rs[43] uses I/O standard 2.5 V at D15
    Info: Pin rs[47] uses I/O standard 2.5 V at AA16
    Info: Pin rs[44] uses I/O standard 2.5 V at P16
    Info: Pin rs[45] uses I/O standard 2.5 V at M21
    Info: Pin rs[46] uses I/O standard 2.5 V at N22
    Info: Pin rs[42] uses I/O standard 2.5 V at N21
Info: Generated suppressed messages file E:/Muxplux/Vhdl/DES/test.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 8 warnings
    Info: Allocated 325 megabytes of memory during processing
    Info: Processing ended: Sun Aug 05 19:14:34 2007
    Info: Elapsed time: 00:00:25


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/Muxplux/Vhdl/DES/test.fit.smsg.