pp.fit.rpt

DES加密算法的VHDL实现,采用流水线技术实现

Fitter report for pp
Sun Aug 05 22:01:04 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Resource Usage Summary
  5. Input Pins
  6. Output Pins
  7. I/O Bank Usage
  8. Output Pin Default Load For Reported TCO
  9. Fitter Resource Utilization by Entity
 10. Delay Chain Summary
 11. Pad To Core Delay Chain Fanout
 12. Non-Global High Fan-Out Signals
 13. Interconnect Usage Summary
 14. Fitter Device Options
 15. Advanced Data - General
 16. Advanced Data - Placement Preparation
 17. Advanced Data - Placement
 18. Advanced Data - Routing
 19. Fitter Messages
 20. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; Fitter Summary                                                           ;
+-------------------------------+------------------------------------------+
; Fitter Status                 ; Successful - Sun Aug 05 22:01:04 2007    ;
; Quartus II Version            ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name                 ; pp                                       ;
; Top-level Entity Name         ; pp                                       ;
; Family                        ; Stratix III                              ;
; Device                        ; EP3SL50F484C2                            ;
; Timing Models                 ; Preliminary                              ;
; Logic utilization             ; 0 %                                      ;
;     Combinational ALUTs       ; 0 / 38,000 ( 0 % )                       ;
;     Memory ALUTs              ; 0 / 19,000 ( 0 % )                       ;
;     Dedicated logic registers ; 0 / 38,000 ( 0 % )                       ;
; Total registers               ; 0                                        ;
; Total pins                    ; 64 / 296 ( 22 % )                        ;
; Total virtual pins            ; 0                                        ;
; Total block memory bits       ; 0 / 1,880,064 ( 0 % )                    ;
; DSP block 18-bit elements     ; 0 / 216 ( 0 % )                          ;
; Total PLLs                    ; 0 / 4 ( 0 % )                            ;
; Total DLLs                    ; 0 / 4 ( 0 % )                            ;
+-------------------------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; AUTO                           ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Auto RAM to MLAB Conversion                                           ; On                             ; On                             ;
; Equivalent RAM and MLAB Power Up                                      ; Auto                           ; Auto                           ;
; Programmable Power Technology Optimization                            ; Automatic                      ; Automatic                      ;
; Programmable Power Maximum High-Speed Fraction of Used LAB Tiles      ; 1.0                            ; 1.0                            ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;