📄 test.sta.rpt
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TimeQuest Timing Analyzer report for test
Sun Aug 05 19:14:41 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Board Trace Model Assignments
4. Slow Corner Signal Integrity Metrics
5. Setup Summary
6. Hold Summary
7. Recovery Summary
8. Removal Summary
9. Unconstrained Paths
10. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+--------------------------------------------------+
; Quartus II Version ; Version 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name ; test ;
; Device Family ; Stratix III ;
; Device Name ; EP3SL50F484C2 ;
; Timing Models ; Preliminary ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Enabled ;
+--------------------+--------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+--------+--------------+---------------+----------------+------------------+--------+--------------+--------------------+--------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; Pin ; I/O Standard ; Near Series R ; Near Pull-up R ; Near Pull-down R ; Near C ; Tline Length ; Tline L per Length ; Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
+--------+--------------+---------------+----------------+------------------+--------+--------------+--------------------+--------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; so[31] ; 2.5 V ; short ; open ; open ; open ; 0 ; 0 ; 0 ; short ; open ; open ; open ; 0 ; - ;
; so[30] ; 2.5 V ; short ; open ; open ; open ; 0 ; 0 ; 0 ; short ; open ; open ; open ; 0 ; - ;
; so[29] ; 2.5 V ; short ; open ; open ; open ; 0 ; 0 ; 0 ; short ; open ; open ; open ; 0 ; - ;
; so[28] ; 2.5 V ; short ; open ; open ; open ; 0 ; 0 ; 0 ; short ; open ; open ; open ; 0 ; - ;
+--------+--------------+---------------+----------------+------------------+--------+--------------+--------------------+--------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics ;
+--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+-------------------------------------+-------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+------------------------------------+------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Margin on Rise at FPGA Pin ; Ringback Margin on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Margin on Rise at Far-end ; Ringback Margin on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+-------------------------------------+-------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+------------------------------------+------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; so[31] ; 2.5 V ; 0 ; 0 ; 2.37 ; 0.00106 ; 2.8 ; -0.0203 ; 0.484 ; 0.0958 ; 7.69e-011 ; 3.68e-010 ; No ; Yes ; 2.37 ; 0.00106 ; 2.8 ; -0.0203 ; 0.484 ; 0.0958 ; 7.69e-011 ; 3.68e-010 ; No ; Yes ;
; so[30] ; 2.5 V ; 0 ; 0 ; 2.37 ; 0.00106 ; 2.8 ; -0.0203 ; 0.484 ; 0.0958 ; 7.69e-011 ; 3.68e-010 ; No ; Yes ; 2.37 ; 0.00106 ; 2.8 ; -0.0203 ; 0.484 ; 0.0958 ; 7.69e-011 ; 3.68e-010 ; No ; Yes ;
; so[29] ; 2.5 V ; 0 ; 0 ; 2.37 ; 0.00106 ; 2.8 ; -0.0203 ; 0.484 ; 0.0958 ; 7.69e-011 ; 3.68e-010 ; No ; Yes ; 2.37 ; 0.00106 ; 2.8 ; -0.0203 ; 0.484 ; 0.0958 ; 7.69e-011 ; 3.68e-010 ; No ; Yes ;
; so[28] ; 2.5 V ; 0 ; 0 ; 2.37 ; 0.00106 ; 2.8 ; -0.0203 ; 0.484 ; 0.0958 ; 7.69e-011 ; 3.68e-010 ; No ; Yes ; 2.37 ; 0.00106 ; 2.8 ; -0.0203 ; 0.484 ; 0.0958 ; 7.69e-011 ; 3.68e-010 ; No ; Yes ;
+--------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+-------------------------------------+-------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+------------------------------------+------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-----------------
; Setup Summary ;
-----------------
No paths to report.
----------------
; Hold Summary ;
----------------
No paths to report.
--------------------
; Recovery Summary ;
--------------------
No paths to report.
-------------------
; Removal Summary ;
-------------------
No paths to report.
+------------------------------------------------+
; Unconstrained Paths ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 4 ; 4 ;
; Unconstrained Input Port Paths ; 16 ; 16 ;
; Unconstrained Output Ports ; 0 ; 0 ;
; Unconstrained Output Port Paths ; 0 ; 0 ;
+---------------------------------+-------+------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Sun Aug 05 19:14:39 2007
Info: Command: quartus_sta test -c test
Info: qsta_default_script.tcl version: 24.0.1.7
Critical Warning: SDC file not found: 'test.sdc'
Info: No base clocks found in the design. Calling "derive_clocks -period 1.0"
Warning: No clocks defined in design.
Warning: Command report_clocks could not find any constraints or exceptions to report
Warning: Command report_clock_fmax_summary could not find any constraints or exceptions to report
Info: No setup paths to report
Info: No hold paths to report
Info: No recovery paths to report
Info: No removal paths to report
Warning: Command report_min_pulse_width could not find any constraints or exceptions to report
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
Info: Allocated 114 megabytes of memory during processing
Info: Processing ended: Sun Aug 05 19:14:41 2007
Info: Elapsed time: 00:00:02
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