l0r0.vhd

来自「DES加密算法的VHDL实现,采用流水线技术实现」· VHDL 代码 · 共 15 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity L0R0 is
port( 	din : in 		std_logic_vector( 1 to 64 );
		l0,r0  : out 	std_logic_vector( 1 to 32 )
	) ;
end L0R0 ;
architecture arch_L0R0 of L0R0 is
begin
	l0 <= din(  1 to 32 ) ;
	r0 <= din( 33 to 64 ) ;

end architecture arch_L0R0 ;